4-Layer PCB Design: stackups, impedance targets, and routing rules

A practical 4-layer PCB design uses an S/GND/PWR/S stackup with controlled 50 Ω single-ended and 90 Ω differential channels, solid return paths, and manufacturable via geometry.

Recommended 4-layer stackups

• 1.6 mm FR-4 (outer microstrip focus): L1 35 µm copper, L1–L2 dielectric ≈ 0.20 mm (e.g., 2116 + 7628), L2 GND plane, L2–L3 core ≈ 1.0 mm, L3 PWR plane, L3–L4 dielectric ≈ 0.20 mm (2116 + 7628), L4 35 µm copper. FR-4 Dk ≈ 3.7–4.2 at 1 GHz

• 1.0 mm FR-4 (thinner microstrip): L1 35 µm, L1–L2 dielectric ≈ 0.14 mm (e.g., 1080 + 2116), L2 GND, L2–L3 core ≈ 0.60 mm, L3 PWR, L3–L4 dielectric ≈ 0.14 mm, L4 35 µm

Both keep high-speed signals on L1/L4 as microstrips referenced to L2 ground to avoid thick-core striplines on L2/L3

What trace widths hit 50 Ω and 90 Ω?

For 35 µm copper and FR-4 Dk ≈ 4.0:

• h ≈ 0.20 mm (outer microstrip): 50 Ω width ≈ 0.30–0.40 mm. 90 Ω differential: width ≈ 0.30–0.35 mm, gap ≈ 0.30–0.40 mm

• h ≈ 0.14 mm (outer microstrip): 50 Ω width ≈ 0.22–0.28 mm. 90 Ω differential: width ≈ 0.20–0.25 mm, gap ≈ 0.20–0.25 mm

Copper thickness, resin content, and soldermask over microstrip shift these values; validate with a field solver or your fabricator’s stackup calculator (IPC-2141A formulas are a reasonable first estimate). Typical controlled-impedance production tolerance is ±10% unless otherwise specified

Plane strategy and decoupling

Use L2 as an unbroken ground reference. Put main rails on L3, keeping splits far from any high-speed path’s return. Stitch copper around board edges to form a low-inductance ground fence (via pitch ≈ 2–4 mm for GHz edges). Place 0.1 µF decouplers within 2–3 mm of each IC power pin with one via to power and one to ground; add bulk 4.7–47 µF per rail cluster. If a signal must cross a power split, add a stitching capacitor (e.g., 0.1 µF) to provide an AC return path

Via choices and clearances

Through vias are the norm on 4-layer:

• Finished hole Ø ≈ 0.25–0.30 mm; pad Ø ≈ 0.55–0.65 mm gives ≥0.15 mm annular ring

• Plane antipad clearance ≈ 0.30–0.40 mm to control capacitance and meet fab rules

• For 1.6 mm boards, via stubs are ≈ 1.6 mm; quarter-wave resonance sits >20 GHz (FR-4), so backdrill is rarely needed below multi‑GHz serial links

For differential pairs, avoid via count; if unavoidable, match via count per line and keep anti-pads identical. Use teardrops on fine geometries to improve yield

Should high-speed routes stay on outer layers?

Often yes on a 4-layer with a thick center core. Outer microstrips over a solid L2 ground give predictable 50/90 Ω and tight return loops. Avoid routing high-speed across plane splits; keep at least 3W spacing between aggressor and victim for crosstalk control (5W if rise-times are very fast). Maintain pair symmetry; on FR-4 the delay is ≈150–180 ps/in, so translate any skew budget in ps to length in mm before length matching

Fabrication and acceptance at HyperPCB

We build to IPC Class 2 or Class 3 acceptance criteria on request and support RoHS/REACH-controlled builds. Our ISO 9001:2015-certified QMS (SGS CN-2023-Q1156, valid to Jun 2027) governs production. Quotes are typically returned within 24 hours and DFM feedback within 1 business day. For RF 4-layer designs that need low-loss or low-Dk materials, our partner factory also manufactures high-frequency laminates used by RF PCB fabricators in China

Practical routing notes

• Keep clocks and fast edges ≥ 10h from board edges (h = dielectric height to reference plane)

• Use ground-referenced guard traces with via stitching for sensitive analog inputs

• Pour top/bottom copper tied to GND with thermal reliefs; set pour-to-trace clearance ≥ 0.20–0.25 mm unless impedance modeling requires tighter

• If outer copper is heavily plated, adjust impedance widths narrower to compensate for thicker conductors

• Document targets: stackup layer order, dielectric thicknesses, Dk/Df, copper weights, trace width/space, pair gap, and impedance tolerances; this avoids surprises in CAM