AP63203 reads ~2.3 V and keeps hiccuping — what to check and how to fix

Why the DMM shows ~2.3 V in hiccup

The AP63203 is repeatedly attempting startup, then shutting down on a protection event. A DMM integrates these bursts, so you see an average near 1–3 V instead of a regulated rail. Confirm with an oscilloscope: during each retry you’ll see SW switch near its nominal MHz range for a short burst, VOUT partially climbs, then EN/SW go quiet for a cool‑down/retry interval before the next attempt.

What fault is it, exactly

Decide whether the first trip is over‑current/short, undervoltage lockout (UVLO), or over‑temperature (OTP). Probe at the IC pins, not the connector. If VIN sags to about the UVLO threshold right before shutdown, it’s supply droop. If SW on‑time grows each cycle until it clamps, then a long blanking period follows, it’s over‑current. If off‑time lengthens as the device heats, suspect OTP.

Scope captures that separate OCP, UVLO, OTP

• VIN at the IC, VOUT at the output capacitor, SW, FB, EN. Use 10× probes, >100 MHz bandwidth, short ground springs.

• Short‑event/OCP: SW shows increasing on‑time within a burst; VOUT barely rises; EN toggles low after a few hundred microseconds; several‑millisecond dead time.

• UVLO: VIN dips at the AP63203 pins right before each stop; the dip aligns with the heaviest SW on‑time within the burst.

• Thermal: duty recovers if you cool the package; off‑times grow with temperature. Log case temperature vs off‑time.

Does your inductor or IC hit current limit

Inductor ripple current (continuous mode):

ΔIL ≈ VOUT × (VIN − VOUT) / (L × VIN × fS)

Peak current: IPEAK ≈ ILOAD + ΔIL/2

Example, 12 V → 3.3 V, fS ≈ 1.1 MHz:

• L = 2.2 µH → ΔIL ≈ 1.0 A; IPEAK at 1.5 A load ≈ 2.0 A.

• L = 1.0 µH → ΔIL ≈ 2.2 A; IPEAK at 1.5 A load ≈ 2.6 A (likely to trip OCP or saturate a small inductor).

Ensure IPEAK stays below the AP63203 current limit (use the datasheet value) and below the inductor’s saturation current across tolerance and temperature.

Startup inrush and soft‑start math

Charging Cout during soft‑start draws IINRUSH ≈ Cout × VOUT / tSS (ignores ESR and load). With Cout = 220 µF, VOUT = 5 V, tSS = 1 ms, IINRUSH ≈ 1.1 A, plus any load current. If the load also starts hard (e.g., a downstream bulk rail), the AP63203 can hit current limit and hiccup. To reduce inrush: increase L, lengthen soft‑start (if available), stagger downstream rail startup, or reduce Cout/ESR.

Is VIN drooping through cables or planes

Estimate line drop during startup: VDROP ≈ ISTART × RPATH. A modest 0.25 Ω round‑trip (cable + connector + plane) at 1.5 A causes ~0.38 V dip. If the adapter is marginal or the input ceramics are not right at the IC pins, the dip can push VIN into UVLO right when SW duty is highest. Place at least 2× 10 µF X7R ceramics within 2–3 mm of VIN–PGND, then add low‑ESR bulk (e.g., 47–220 µF electrolytic/polymer) at the same nodes.

Feedback, EN, and pre‑bias pitfalls

Route FB away from the SW copper. Kelvin‑connect the bottom FB resistor to a quiet ground near the output capacitor return. If EN is set with a divider, ensure the rising threshold exceeds the worst‑case loaded VIN during ramp, and add hysteresis (for example, 100 kΩ/20 kΩ divider with a 1 MΩ feed‑forward can give a few hundred millivolts of hysteresis; tune to your thresholds). Pre‑biased outputs or hot‑plugging USB loads can look like a short; add a downstream inrush limiter or sequence that rail.

Layout changes that stop hiccup

Keep the hot loop (VIN cap → IC → high‑side switch → SW node → inductor → output cap return → PGND) as tight as possible. Put the highest‑frequency VIN ceramic directly across the IC’s VIN–PGND pins; aim for <2 mm lead length and wide copper. Keep the SW island compact to limit ringing that can corrupt FB/EN. Use a 100 nF X7R boot capacitor at the pins. If ringing remains, add a snubber (start with 1 Ω + 330 pF from SW to PGND, then tune by measurement).

How hot is too hot for this buck

Most monolithic bucks enter OTP around 150 °C junction. Design margin keeps worst‑case Tj ≤ 125 °C. Measure with a fine‑bead thermocouple epoxied to the top package or use an IR camera with known emissivity; correlate temperature with hiccup periodicity. Estimate thermal headroom with Tj ≈ Ta + Ploss × θJA. For small QFN/SOP bucks, θJA on a minimal footprint can exceed 60–80 °C/W; adding 2–4 cm² of 1 oz copper tied to the exposed pad with 6–10 vias (0.3 mm drill) commonly drops θJA by tens of °C/W. If you are within 10–15 °C of OTP at max ambient, add copper area or airflow, or reduce ILOAD.

Component integrity and simple A/B tests

If the rail regulates with the load disconnected, the cause is overload or inrush. Swap in an inductor with higher saturation current and DCR ≤ the original; if hiccup disappears, you were saturating. Replace the boot cap and the output ceramics if they have seen over‑voltage or solder rework. A shorted output cap or a marginal cable is a frequent root cause.

Manufacturing and acceptance options

We build to IPC Class 2 or IPC Class 3 acceptance criteria and support RoHS/REACH compliance. Our ISO 9001:2015 certified quality management system (certificate no. CN-2023-Q1156, issued by SGS, valid until June 2027) governs process control. You can expect a quote within 24 hours and DFM feedback within 1 business day; early DFM often flags risky VIN decoupling placement, SW island size, and FB routing before fab.