4-layer PCB example: stack-up, impedance, routing, and fab notes

Here is a concrete 4-layer PCB example you can reuse: a 1.60 mm FR-4 S–GND–PWR–S stack-up with 50 ohm single-ended, 90 ohm differential targets, and routing rules for USB 2.0 and MCU designs.

Example 4-layer stack-up and target impedances

• Overall thickness: 1.60 mm FR-4 (Tg ≈ 170 C)

• Copper: outer layers finished ~35 µm, inner layers ~18 µm

• L1 (signal) to L2 (GND) dielectric: ~0.18 mm (e.g., 2116 + 1080 prepregs)

• L2 (GND) to L3 (PWR) core: ~1.20 mm FR-4 (Dk ~3.7–4.2 @ 1 GHz)

• L3 (PWR plane) to L4 (signal): ~0.18 mm (2116 + 1080)

• Reference planes: L2 = solid ground; L3 = power plane (avoid splits under high-speed)

Impedance targets on outer microstrips (reference L2):

• 50 ohm single-ended (L1/L4): with h ≈ 0.18 mm, t ≈ 35 µm, Dk ≈ 3.9 → width w ≈ 0.31 mm (≈12.2 mil)

• 90 ohm differential (L1/L4): starting values w ≈ 0.20 mm (≈8 mil), spacing s ≈ 0.20 mm (≈8 mil)

Confirm with your fabricator’s field solver; Dk tolerance and resin content can shift impedance by roughly 5–10%.

Why choose S–GND–PWR–S

Both outer layers route as microstrips over a continuous ground (L2), giving well-defined return paths, low crosstalk, and predictable 50/90 ohm control. The power plane (L3) sits close to ground, enabling short decoupling loops; place bulk and high-frequency capacitors on L1/L4 with vias straight into L2/L3. This arrangement also reduces EMI compared with placing a split plane directly under high-speed signals.

How should I route USB 2.0 and clocks on this stack-up?

• USB 2.0 HS pair (D+/D−): route as 90 ohm differential on L1 (or L4) over solid L2; keep spacing s constant through bends and neck-downs. Avoid running the pair across L3 splits. Within-pair length skew ≤ 0.5 mm (≈20 mil) is a conservative target for HS USB.

• Keep-away: ≥ 3× dielectric height to plane (≈3h ≈ 0.54 mm) or ≥ 3× pair spacing to aggressors; more if edges are very fast.

• Vias: minimize. When a layer transition is necessary, place a ground via within 1–2 mm of the signal via to provide a short return path to L2.

• Clocks (50 ohm): keep short, reference L2, avoid splits beneath the trace, and use consistent impedance for stubs into terminations.

What should I put in the fabrication package?

• Gerbers (RS-274X) or ODB++, Excellon drills

• Stack-up table: copper weights and dielectrics (L1–L2 0.18 mm; L2–L3 1.20 mm; L3–L4 0.18 mm), material family and Dk/Df

• Impedance table: 50 ohm microstrip (L1/L4), 90 ohm differential microstrip (L1/L4), tolerance (±10% typical), and coupon requirement

• Drill chart: finished hole sizes, via plating thickness, any backdrill notes if applicable

• Acceptance criteria: IPC Class 2 or IPC Class 3, and the target revision of IPC-6012/IPC-A-600 for inspection

• Finish/mask: ENIG or HASL, solder mask color, legend color, RoHS/REACH statement

• Keepout notes: no high-speed routing over plane splits; stitching vias around high-speed regions

Cost and risk drivers you can control

Overall cost is most sensitive to minimum trace/space, smallest drill size and count, copper weight, impedance tolerance, and finishes. Tighter impedance windows (e.g., ±5% vs ±10%) and very small finished holes (<0.25 mm) increase scrap risk and cycle time. Keeping USB pairs on one outer layer with few vias, specifying standard copper (outer ~35 µm, inner ~18 µm), and holding 90 ohm tolerance at ±10% are cost-stable choices for a 4-layer build.

Compliance and build options at HyperPCB

HyperPCB operates an ISO 9001:2015 certified quality management system (SGS certificate CN-2023-Q1156, valid through June 2027). Boards can be built and inspected to IPC Class 2 or Class 3 acceptance criteria. RoHS and REACH compliance is supported for hazardous substance control. Quotes are returned within 24 hours and DFM feedback within one business day.