PCB quote checklist: files, stackups, impedance, DFM

To get a fast, accurate PCB quote, include complete manufacturing data, a clear fab drawing, and a realistic stackup with impedance targets.

Which files get you a fast PCB quote?

• Manufacturing data: Gerber X2 or ODB++, Excellon drills, IPC‑356A netlist, and a readme with CAD/version notes

• Fab drawing: board outline, overall thickness (e.g., 1.0/1.2/1.6 mm), layer count, per‑layer copper (e.g., 1 oz outer / 0.5 oz inner), material family (FR‑4 Dk/Df range or RF laminate), solder mask and legend colors

• Stackup/impedance: dielectric thickness per layer, Dk/Df targets or allowed range, reference planes, impedance goals (e.g., 50 Ω single‑ended; 90/100 Ω differential) and tolerance (±10% typical); note if solder mask is opened over controlled‑impedance traces

• Design rules: minimum trace/space (call out if ≤3/3 mil; 4/4 mil is a common cost baseline), minimum annular ring (finished ≥4 mil), smallest drills (mechanical finished ≥0.25 mm; laser microvia ≈0.10 mm), via types (through, blind/buried, microvia), via fill/cap requirements

• Surface finish: lead‑free HASL, ENIG, immersion silver; for ENIG, specify Ni 3–6 µm and Au 0.04–0.10 µm if wear or wire‑bonding matters

• Testing/acceptance: 100% electrical test, IPC‑6012 Class 2 or Class 3, impedance coupons and any special coupons

• Panelization: deliverable panel size, 5–10 mm rails, global fiducials, 2–3 mm tooling holes; or permit fabricator panelization around common 18×24 in or 21×24 in working panels

• Quantities/variants: prototype vs volume lots, any impedance coupon count, ship‑to region

• For assembly (if needed): BOM with MPNs/alternates and DNP flags, centroid (CSV/XY), assembly drawing

Controlled impedance: what should you specify?

Tie targets and tolerances to a feasible stackup (IPC‑2141 or a field solver). Example FR‑4 figures often used around 1 GHz (Dk ≈ 3.8–4.1):

• 4‑layer, ~1.6 mm overall, L1–L2 dielectric ≈0.18–0.20 mm, 1 oz outer copper: 50 Ω microstrip typically lands near 12–16 mil width with solder mask present; note if you open mask over these traces because mask raises εeff and lowers Z0 for a given width.

• 100 Ω differential stripline on inner layers with ≈0.18–0.20 mm dielectric per side and 0.5 oz inner copper: pairs commonly use ~4–5 mil lines with ~8–10 mil spacing.

• 90 Ω differential microstrip (e.g., USB 2.0 HS) on the top layer over ≈0.18–0.20 mm dielectric: widths ~7–9 mil with ~7–10 mil spacing are typical, adjusted for mask coverage.

Always request fabricator‑confirmed stackups and impedance coupons with the lot.

What drives price and lead time?

Costs step up when designs push manufacturing limits:

• Trace/space: ≤3/3 mil moves into HDI; 4/4 mil is a common low‑risk baseline.

• Drilling: mechanical finished holes <0.25 mm increase tool wear and hit rate; <0.20 mm often requires special processes. Plated‑through aspect ratio >8:1 (board thickness ÷ finished hole) adds risk and cost; e.g., 1.6 mm with 0.15 mm holes is ~10.7:1.

• Copper: outer or inner layers >1 oz/ft² need longer etch/plating cycles; heavy copper (2–3 oz) compounds this.

• HDI features: blind/buried vias, stacked microvias, backdrill, edge plating, and castellations add process steps.

• Tolerances: tighter overall thickness (e.g., ±0.08 mm vs ±0.15 mm), bow and twist ≤0.5% (vs 0.75%), or hole tolerance tighter than ±3 mil finished can increase cycle time.

• Finish: ENIG adds Ni/Au deposition and tighter cleanliness controls versus lead‑free HASL; specify exact thickness if functionally critical.

• Panel utilization: ask for re‑panelization to fit common 18×24 in or 21×24 in working panels; matching deliverable panels to these sizes reduces scrap and fixture count.

DFM details that prevent requotes

• Solder mask: dam ≥4 mil where possible; mask expansion ≈3–4 mil around pads to avoid slivers.

• Clearances: NPTH copper‑to‑hole ≥10 mil; copper‑to‑board edge (rout) ≥0.20 mm (8 mil) unless otherwise agreed; plane pullbacks around slots and edges.

• Vias‑in‑pad: for ≤0.50 mm BGA pitch, specify via fill and planar cap before ENIG to prevent wicking; state fill type (resin/epoxy) and any reliability tests (e.g., IST).

• Drills: provide a drill chart with tool counts, plated vs NPTH, finished sizes, and tolerances (commonly ±3 mil finished for PTH); call out backdrill depths and keepouts.

• Coupons and tests: request impedance and microsection coupons when impedance control or HDI is present; state IPC‑6012 Class 2 or Class 3 acceptance.

Verified capabilities and response at HyperPCB

HyperPCB operates an ISO 9001:2015 certified quality management system (certificate no. CN‑2023‑Q1156, issued by SGS, valid until June 2027). Quotes are returned within 24 hours and DFM feedback within 1 business day. Boards can be built and inspected to IPC Class 2 or IPC Class 3, and RoHS/REACH compliance is supported. Our partner factory AEGIS maintains ISO 9001:2015, ISO 14001:2015, and ISO 45001:2018, and also holds ISO 13485:2016 and IATF 16949. Our partner factory manufactures its own high‑frequency laminates and supplies RF PCB fabricators in China, including publicly listed PCB companies.