PCB prototype simulator: what to run before you fab

A PCB prototype simulator is the set of circuit, signal, power, and EM analysis tools you run to predict if your first build meets electrical and thermal requirements before you pay for fabrication.

What “PCB prototype simulator” really means

In practice it’s not one program. You combine SPICE for circuits, transmission-line and field solvers for impedance/crosstalk, IBIS- or SPICE-based I/O models for links, PDN solvers for power rails, plus quick thermal and EMI screens. The goal is to find first-order failures early: impedance misses, ringing, eye closure, rail droop, and hot spots.

Which simulations matter first?

• Schematic-level SPICE: verify biasing, stability, and transient limits

• I/O model sims (IBIS/SPICE): reflections, overshoot, eye diagrams

• 2D field solver: trace width/spacing for target Z0 and Zdiff

• PDN impedance: decoupling strategy to hold Z under target

• Basic thermal: package-to-board theta, via arrays, plane spreading

• EMI return-path checks: gaps, slots, stubs, and common-mode sources

How wide for 50Ω and 90Ω on FR‑4?

Use a 2D field solver or IPC‑2141 equations for first pass, then lock values with the exact stackup from your fabricator.

Example microstrip (top over plane):

• Dielectric height h ≈ 0.18 mm (common 2116/7628 build-up), copper t ≈ 35 µm, Dk ≈ 3.9 at 1 GHz

• Single‑ended 50Ω typically needs width W ≈ 0.30–0.36 mm (12–14 mil)

• Differential 90Ω often lands near W ≈ 0.15–0.18 mm (6–7 mil) with gap S ≈ 0.15–0.20 mm (6–8 mil)

Example symmetric stripline (signal between two planes):

• Core-to-plane distance each side h ≈ 0.10–0.12 mm, Dk ≈ 3.8–4.0

• Single‑ended 50Ω often needs W ≈ 0.18–0.22 mm (7–9 mil)

• Differential 100Ω around W ≈ 0.14–0.18 mm (5.5–7 mil) with S ≈ 0.14–0.20 mm (5.5–8 mil)

Adjust for copper thickness, resin content (e.g., 7628 vs 2116), roughness, and frequency. Always re-solve with your final stackup and ask for controlled-impedance fabrication with a tolerance such as ±10%.

Do I need 3D EM for my prototype?

Use 3D EM for structures where 2D assumptions break: antennas, waveguides, via fields above ~5–10 GHz, tight couplers, complex launch transitions, or when package/connector geometry dominates. For most sub‑10‑Gbps digital links on uniform stripline/microstrip, a good 2D solver plus via models and vendor IBIS is usually sufficient for a first build.

What PDN impedance is “good enough”?

Set a target impedance Ztarget = Vripple_max / Itransient_max. Example: a 1.0 V rail with 50 mV allowable ripple and a 2 A step gives Ztarget = 0.05 / 2 = 25 mΩ. Keep |Z| under 25 mΩ from low frequency up to roughly 0.35 / tr of the load (tr in seconds). With tr = 1 ns, that’s about 350 MHz. Model capacitor ESL/ESR and mounting inductance; a few 0402 MLCCs close to the pins often dominate above ~50–100 MHz.

Thermal and EMI quick screens

Assume FR‑4 in‑plane thermal conductivity near 0.3 W/m·K; rely on copper planes and via arrays under hot ICs to move heat. A 5×5 mm QFN dissipating 2 W typically benefits from a stitched thermal pad with ~9–16 vias of finished 0.2–0.3 mm to a solid plane. For EMI, ensure uninterrupted return paths under fast nets, avoid stubs, and bridge any plane splits with capacitors or reroutes; small changes here often remove a common-mode peak.

Tool options that cover the bases

Free or low-cost: LTspice/Ngspice for circuits, KiCad’s PCB calculator or Saturn PCB Toolkit for first-pass impedance, and vendor IBIS models for I/O. Commercial: 2D field solvers (e.g., Polar-class tools) for accurate W/S, SI/PI suites (HyperLynx, Sigrity, ADS) for eyes and PDN, and 3D EM (HFSS/CST) when geometry demands it.

From simulator to fabrication

Package these in your fab notes:

• Stackup drawing with each dielectric thickness, copper weight, and Dk/Df at a stated frequency

• Controlled-impedance callouts by net class, with target and tolerance (e.g., 50Ω SE ±10%, 90Ω diff ±10%)

• Min trace/space and drill sizes that your layout actually uses

• Specify soldermask type and finish where signal loss matters (mask over microstrip changes Z0)

Include reference designs for edge launches or test coupons if you will measure with TDR or VNA.

Post‑build checks to correlate results

• TDR on controlled‑impedance coupons or accessible runs to confirm Z0/Zdiff and discontinuities

• Eye or BER on a stressed pattern for high‑speed links; correlate with simulated bathtub curves

• Step‑load test on major rails to verify PDN overshoot and settling

• Simple IR camera or thermocouple on hot ICs to compare against thermal estimates

How HyperPCB fits into this plan

For builds that must follow documented quality processes, our quality management system is ISO 9001:2015 certified (certificate CN-2023-Q1156 by SGS, valid to June 2027). We return quotes within 24 hours and DFM feedback within 1 business day, so you can iterate stackups and impedances quickly. Boards can be built and inspected to IPC Class 2 or Class 3 acceptance criteria, and RoHS/REACH compliance is supported. For RF prototypes requiring low‑loss dielectrics, our partner factory AEGIS manufactures its own high‑frequency laminates and supplies RF PCB fabricators in China; AEGIS also maintains ISO 9001:2015, ISO 14001:2015, and ISO 45001:2018, plus ISO 13485:2016 and IATF 16949 for regulated sectors.