What is a 4‑layer PCB machine? Equipment, process, and build specs

There isn’t a single “4‑layer PCB machine”; a 4‑layer board is built by a coordinated line that images, laminates, drills, plates, etches, coats, finishes, and tests the PCB. If you’re sourcing, focus on stackup, impedance, acceptance class, and test coverage—not on any one piece of equipment.

Is there a single 4‑layer PCB machine?

• Inner-layer imaging and etch: LDI/UV exposure, cupric/alkaline etch, post-etch AOI

• Oxide/adhesion: brown/oxide alternative treatment on inner copper

• Layup and lamination: vacuum lamination press, typical FR‑4 Tg 150–170°C cure; pressed cycles ~170–190°C with controlled ramp/soak and 1–2 MPa platen pressure depending on resin

• Drilling: NC mechanical drills (e.g., 0.2–0.3 mm finished hole) and routing; optional backdrill

• Hole wall prep: desmear/etchback (KMnO4 or plasma)

• Copper deposition: electroless Cu seed (~0.5–1.0 µm), acid Cu plate to ~20–25 µm in holes when needed

• Outer-layer pattern: LDI/expose, pattern plate, etch, final AOI

• Solder mask: spray or curtain coat, image, cure; min dam commonly ≥0.10 mm (4 mil)

• Surface finish: ENIG (Ni 3–7 µm, Au 0.05–0.1 µm), HASL, OSP, or others

• Marking and profile: legend print, route/laser

• Electrical test: flying probe or fixture netlist test; final inspection per IPC class

Typical 4‑layer stackups and impedance targets

A common 1.6 mm build uses symmetric dielectric and copper:

• Example A (1.6 mm): L1 35 µm / PP stack (e.g., 2116+7628, pressed ~0.22–0.28 mm) / L2 18–35 µm // Core ~0.8 mm FR‑4 // L3 18–35 µm / PP (2116+7628 ~0.22–0.28 mm) / L4 35 µm. With outer dielectric ~0.20–0.25 mm to L2/L3, 50 Ω microstrip on L1 is typically ~0.33–0.38 mm width (35 µm Cu, Er 3.6–3.9). A 100 Ω differential microstrip often lands near 0.18/0.18 mm (w/space), while 90 Ω is ~0.20/0.20 mm; verify with a field solver.

• Example B (1.0 mm): Reduce core (e.g., ~0.4–0.5 mm) and use thinner PP (e.g., 2113/2116 pressed ~0.12–0.18 mm) to maintain similar impedances with smaller widths. 50 Ω stripline (centered between ~0.20 mm dielectrics) tends to be ~0.24–0.28 mm width with 35 µm Cu.

Glass styles (e.g., 7628 ≈ 0.18 mm pressed, 2116 ≈ 0.10–0.12 mm) and resin content change Dk/Df and thickness; always lock the target stackup in the RFQ and request an impedance coupon.

Design rules that keep yield high

For mainstream wet-process lines, start with 4/4 mil (0.10/0.10 mm) trace/space and 0.30 mm finished vias; many shops can run 3/3 mil and 0.25 mm vias at added cost/risk. Maintain annular ring ≥0.10 mm (4 mil) and copper-to-board-edge ≥0.30 mm. Outer copper 35 µm is common; inner 18–35 µm. Keep via-to-copper features ≥0.25–0.30 mm for drill wander and plating margin. Aspect ratio ≤8:1 improves PTH reliability (e.g., 1.6 mm board with ≥0.20 mm drill).

Can I build 4‑layer boards with desktop tools?

Not realistically. Four-layer requires vacuum lamination with controlled resin flow, hole-wall desmear/etchback, electroless/electrolytic copper, and tight registration and AOI. Milling/toner transfer workflows are feasible for simple 2‑layer prototypes, but through‑hole plating and multilayer lamination are industrial processes.

Standards, compliance, and what we certify

We build and inspect to IPC Class 2 or IPC Class 3 acceptance criteria (e.g., per IPC‑6012/IPC‑A‑600). A documented ISO 9001:2015 quality management system is in place (certificate CN-2023-Q1156, issued by SGS, valid through June 2027). RoHS and REACH compliance is supported when specified. Our partner factory AEGIS maintains ISO 9001:2015, ISO 14001:2015, and ISO 45001:2018; it also maintains ISO 13485:2016 (medical) and IATF 16949 (automotive). AEGIS manufactures its own high‑frequency laminates and supplies RF PCB fabricators in China, including publicly listed companies.

What to include in an RFQ for 4‑layer PCBs?

Provide Gerber/ODB++ and a target stackup (glass styles or dielectric thicknesses), controlled‑impedance nets and targets (e.g., 50 Ω, 90/100 Ω diff) with copper weights, finished thickness (e.g., 1.0 mm, 1.6 mm), surface finish (ENIG, HASL, etc.), minimum trace/space and via sizes, via treatment (tented, plugged, via‑in‑pad), solder mask color and min dam, silkscreen, acceptance class (IPC Class 2 or 3), RoHS/REACH requirements, test coverage (100% netlist E‑test), panelization instructions, and any coupons.

Sourcing notes that reduce risk

Specify impedance on the fab drawing and ask for solver‑checked widths; require coupons measured to target. For power planes, allow ≥20–25 µm copper in holes if high current. Note copper balancing (thieving) and keep symmetric dielectric around the core to limit bow/twist. We return quotes within 24 hours and DFM feedback within 1 business day so you can validate manufacturability before release.