Assess PCB feasibility from dimensions and total component area

Compute the placement density as total component courtyard area divided by usable PCB area, then check routing, assembly/test, and fabrication limits against concrete thresholds.

Define usable area and placement density

Start with usable board area Au. Subtract edge copper keepouts (0.25–0.5 mm), mounting holes, slots, and stiffener keepouts. Example: 100×50 mm board with 0.5 mm edge keepout → Au ≈ (99×49) = 4851 mm² after also deducting two 3.2 mm holes and their 1.5 mm keepouts.

Compute placement density f = Acomponents_courtyard / Au, where each component’s courtyard extends beyond body/pads per IPC-7351 (typical +0.25 mm; use +0.5 mm for connectors/heatsinks). Thresholds that correlate well with buildability:

• f ≤ 0.50: comfortable on one side; routing usually straightforward on 4–6 layers for mixed-signal designs.

• 0.50 < f ≤ 0.70: feasible but requires disciplined keepouts and test access; routing likely needs 6+ layers for high I/O.

• 0.70 < f ≤ 0.85: tight; expect HDI features, microvias, or more layers; DFM risks rise.

• f > 0.85: generally not feasible without shrinking packages, moving to both sides, or enlarging the PCB.

If you can place on both sides, use an effectiveness factor k for the bottom side (k ≈ 0.6–0.9 depending on bottom-side part sizes and reflow constraints). Effective area Aeff ≈ Atop + k·Abot; if both sides are same size, Aeff ≈ (1 + k)·Au. Example: Au = 4524 mm², Acomponents = 3200 mm², k = 0.7 → Aeff = 1.7·4524 = 7689 mm² → feff = 0.42 (comfortable).

Will it route on your target stackup?

Placement fit is necessary, but escape and channel capacity decide feasibility.

• Through‑hole vias on 1.6 mm FR‑4 with 0.20 mm finished drill give aspect ratio ≈ 8:1, a common upper limit for standard plating; 0.25–0.30 mm drills are more forgiving. If thickness increases, keep aspect ratio ≤ 8–10:1 or move to stacked microvias.

• With 4/4 mil (0.10/0.10 mm) trace/space, a 0.8 mm BGA typically allows one escape track between pads; 0.5 mm BGA generally needs microvias (via‑in‑pad or dogbone with 0.1–0.15 mm laser vias) and ≥ 6–8 layers.

• A quick pin‑density check: Dp = total I/O pins per cm² of Au. As a rule of thumb, 4‑layer, 4/4 mil boards are comfortable below ~40 pins/cm²; 6–8 layers handle ~60–120 pins/cm² if fan‑out uses vias efficiently. Mixed analog/power reduces effective capacity.

• Power/ground planes consume layers early. If you budget two planes plus four signal layers, keep fine‑pitch BGAs limited or adopt HDI for the inner rows.

Do assembly and test access still fit?

Courtyard fit doesn’t guarantee manufacturability:

• Maintain at least 0.5 mm courtyard‑to‑courtyard clearance for small passives; ~1.0 mm around tall parts improves pick‑and‑place yield.

• Keep copper ≥ 0.25–0.5 mm from the routed edge; reserve 2–3 mm near edges for tall connectors, card guides, or press‑fit zones.

• Global fiducials: 3 per side, 1.0 mm copper with ~2.0–3.0 mm clearance is common. Local fiducials for fine‑pitch/BGA.

• Plan test access early: a 1.27 mm or 1.00 mm grid for probe pads, or use via‑probe strategy; budget a few percent of area for fixtures and isolation gaps.

• For two‑sided reflow, keep heavy/high‑center‑of‑gravity parts on the top side, or use adhesives/carriers if bottom‑side mass is nontrivial.

Power density and thermal headroom

Estimate total dissipation Ptot and area Au to get power density p = Ptot / Au. If p > 0.3–0.5 W/cm² on standard 1 oz copper without forced airflow, expect notable temperature rise and consider thicker copper (2 oz in current paths), thermal vias under hot packages, and dedicated copper islands. Validate with component θJA data and early DC drop/thermal simulations.

Compliance, creepage, and clearances

For low‑voltage digital, 0.20–0.30 mm conductor spacing is commonly manufacturable. For mains or high‑voltage sections, check creepage/clearance per IPC‑2221B/IEC‑60664; expect millimeter‑scale gaps (several mm) depending on voltage, pollution degree, and conformal coating. Don’t let the courtyard sum hide these keepouts—reserve them explicitly in Au.

A fast feasibility checklist you can run now

• Compute Au and f (or feff). If f > 0.7, plan HDI and/or more layers.

• Check pin density vs layer/feature set; flag BGAs ≤ 0.5 mm pitch for microvias.

• Verify aspect ratio with the thinnest planned mechanical drills.

• Allocate fiducials, test pads, and edge/tooling keepouts up front.

• Estimate power density and add copper/thru‑vias where p is high.

What can we verify in 1 day?

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