How to route a medium‑speed SPI bus across a backplane

Route a medium‑speed SPI backplane as 50 Ω controlled‑impedance lines, keep each stub ≤0.6 in for 1 ns edges, add 25–35 Ω source series resistors, interleave grounds in the connector, and prove a timing budget with ≥20% margin.

What counts as medium speed on a backplane?

For CMOS SPI with 3.3 V drivers, 5–40 MHz is common, but the edge (≈1–3 ns) dictates signal‑integrity risk. Once edges are a few nanoseconds and the interconnect spans tens of inches plus a connector, treat every net (SCLK, MOSI, each MISO) as a transmission line with controlled impedance and managed returns.

Timing budget with a concrete backplane example

Use FR‑4 velocity v ≈ 150–170 ps/in (≈6–6.7 in/ns). For SPI Mode 0/3 the receiver effectively has about half a clock period, T/2, to satisfy setup/hold. Define one‑way lengths from master to a slot as Lfwd and from that slot back to the master as Lret. Then tclk ≈ Lfwd·0.17 ns/in, tmosi ≈ Lfwd·0.17 ns/in, tmiso ≈ Lret·0.17 ns/in. Constraints:

MOSI: T/2 > |tclk − tmosi| + tSU,slave + jitter.

MISO: T/2 > tclk + tmiso + tCO,slave + tSU,master + jitter.

Worked case: a 12 in backplane field plus 4 in on each card gives Lfwd ≈ 16 in → tclk ≈ 2.7 ns. The return path from the slot is similar: tmiso ≈ 2.7 ns. With tCO,slave = 6 ns, tSU,master = 2 ns, and 0.5 ns combined jitter, MISO needs T/2 > 2.7 + 2.7 + 6 + 2 + 0.5 = 13.9 ns → fMAX ≈ 1/(2·13.9 ns) ≈ 36 MHz. Reserve ≥20% margin for temperature, Dk spread, and aging; a practical target is ≤25–30 MHz for this geometry.

Topology and stub control

Use point‑to‑point or daisy‑chain; only one device may ever drive MISO at a time, with all others tri‑stated. Limit every stub to lstub ≤ v·tr/10. With tr = 1 ns and v ≈ 6 in/ns, lstub ≤ 0.6 in; with 0.5 ns edges, lstub ≤ 0.3 in. If device edges are very fast, increase source resistance to slow the edge and damp reflections rather than accepting long stubs.

How should I terminate SPI on a backplane?

Design single‑ended 50 Ω to a solid reference (microstrip or stripline). Series‑terminate at the source: Rs ≈ Z0 − Rdriver. With Z0 ≈ 50 Ω and a CMOS output resistance of 15–25 Ω, pick Rs ≈ 25–35 Ω for SCLK, MOSI, and at each MISO source on the slot. Avoid parallel terminations in multidrop because they load the bus; keep pull‑ups/pull‑downs weak (e.g., tens of kilohms) for idle definition. If you scope >10–15% overshoot/undershoot of VDD at the far end, raise Rs or reduce drive strength until the single‑step response is critically damped.

Connector pinout and return paths

Interleave grounds so each signal always has an adjacent, continuous return across the connector and on the backplane. A compact mapping for one slot is: G SCLK G MOSI | G MISO G CS. Shield SCLK with grounds, keep spacing around SCLK wider than other nets if edges are sub‑nanosecond, and avoid split planes under any SPI route.

How close should SCLK and MOSI be length‑matched?

Keep master‑to‑slave SCLK vs MOSI mismatch ≤0.5 in (≈0.08 ns). That ensures routing skew remains small compared to device timing and your margin lives in T/2 rather than in copper. MISO is a round‑trip path you cannot fully match to SCLK; choose slaves with small tCO for higher f, or add a re‑timing flip‑flop at the slot if you must push frequency.

When should I switch to differential drivers?

Switch to 100 Ω differential transceivers (for SCLK and data) when any of these are true: one‑way reach exceeds ≈24–36 in; edge rate ≤1 ns with two or more populated slots; measured ground shift between slots is >100–200 mV during activity; or your EMI mask is tight and near‑field scans show SCLK as a dominant radiator. A simple screening calculation helps: estimate single‑ended noise margin as VNM ≈ VILmax − Vth_cross, accounting for reflections (Γ = (Zload − Z0)/(Zload + Z0)), crosstalk (scale with spacing; ~3W reduces near‑end crosstalk to a few percent), and ground bounce from simultaneous switching. If VNM falls below a few hundred millivolts, differential buys you common‑mode rejection and predictable termination. When you go differential, maintain pair skew ≤5 mil/in and terminate with 100 Ω at the receiver.

Stackup examples for 50 Ω control

Follow IPC‑2141/IPC‑6012 practices and verify with a field solver using your exact laminate set (e.g., 7628/2116 prepregs) and copper thickness. Typical FR‑4 (Dk ≈ 3.7–4.0, 35 µm copper): microstrip with dielectric to plane ≈0.18 mm yields W ≈0.30–0.35 mm for 50 Ω. Symmetric stripline with ≈0.20–0.25 mm dielectric to each plane yields W ≈0.28–0.33 mm for 50 Ω.

Bring‑up checks that catch most issues

• Measure time‑of‑flight (TDR or step response) and recompute the MISO T/2 budget; keep ≥20% slack at worst‑case Dk and temperature.

• Inspect the step at the far end; adjust Rs until ringing settles within one crossing.

• Verify every stub is within tr·v/10; depopulated slots’ MISOs are tri‑stated.

• Confirm SCLK vs MOSI skew ≤0.5 in per slot; re‑trim if a connector revision changed lengths.

• Scope SCLK at the receiver; keep total jitter <10% UI at the target rate.

Manufacturing and documentation at HyperPCB

Call out controlled impedance (50 Ω single‑ended, 100 Ω differential when used) and IPC Class 2 or Class 3 on your drawings. HyperPCB’s quality management system is ISO 9001:2015 certified (SGS, certificate CN‑2023‑Q1156, valid to June 2027). We support RoHS and REACH substance control, return quotes within 24 hours, and provide DFM feedback within one business day. Boards can be built and inspected to IPC Class 2 or Class 3 acceptance criteria.