Capacitive trackpad PCB review checklist with numeric rules

Here is a numeric checklist to review capacitive trackpad PCBs before release.

Release checklist you can copy‑paste

• Controller and sensing: confirm self‑cap or mutual‑cap per datasheet rev; log firmware/base scan rate used for validation

• Overlay: material and thickness on drawing (e.g., 0.8–1.5 mm polycarbonate); note any OCA/adhesive 50–200 µm

• Electrode geometry: cell pitch 10–14 mm; trace/space 0.20–0.50 mm; uniform pattern across the active area

• Copper‑free moat: ≥3.0 mm from sensor outline; no vias or logos inside the moat

• Under‑pad planes: no solid plane directly under sensors; nearest solid plane recessed 3–5 mm

• Shield (if used): hatch 25–40% copper, 0.5–1.0 mm grid; 0.5–1.0 mm clearance to sensor traces; continuous returns to IC

• Sense line routing: keep <50 mm where possible; 2–3 mm spacing to aggressors; cross unavoidable aggressors at 90°

• Damping at IC: 100–220 Ω series per sense pin; guard rings to quiet ground or driven shield per controller guidance

• USB 2.0: 90 Ω differential ±10%; intra‑pair skew ≤1.25 mm; minimize stubs; ESD diode at connector, Cj <1 pF

• I2C (400 kHz): bus C <400 pF; pull‑ups 2.2–4.7 kΩ; keep bus short and away from sense lines

• ESD plan: design to IEC 61000‑4‑2 (8 kV contact, 15 kV air); stitch GND/chassis vias every 2–3 mm along bezel

• Board edge: copper setback 0.25–0.5 mm; document any chassis bond finger locations

• DFM minima: ≥0.10 mm trace/space; via annular ring ≥0.15 mm; tent or mask‑fill vias under the overlay

• Decoupling: shortest loops at controller; any analog/digital split only if required by the controller datasheet

• Testability: TP for I2C/USB/IRQ/RESET; add GND loops near the touch area for probing

• Documentation: declare stackup, overlay/adhesives, impedance notes (USB 90 Ω diff, any SE targets), RoHS/REACH

• Acceptance: specify IPC Class 2 or Class 3 on the fab/assembly notes

• Sign‑off metrics: baseline C per cell recorded; SNR ≥10:1 on finger touch; noise spectrum checked for 50/60 Hz

Electrodes, keep‑outs, and parasitics

Use consistent cells (diamonds or interdigitated bars) with 10–14 mm pitch so inter‑cell coupling stays predictable. Keep a ≥3 mm copper‑free moat from the sensor outline; if a logo LED is required, push it outside the moat or fully shield it. Avoid any high‑dv/dt or high‑di/dt nets beneath the active area; coupled parasitics here raise baseline C and mask touches.

Do I need ground under the touch area?

Avoid a solid plane under the pad; it increases baseline capacitance and reduces sensitivity. If you must shield, use a hatched or driven shield with 25–40% copper density on a 0.5–1.0 mm grid, keeping 0.5–1.0 mm clearance to sensor traces. Recess the nearest solid plane 3–5 mm from the sensor edge. Where supported, a driven shield directly under the pad with short returns to the IC improves immunity without the sensitivity hit of a static ground plane.

Routing the sensor to the controller without killing SNR

Keep sense lines on the same layer as electrodes to avoid layer swaps under the pad. Hold 2–3 mm spacing to aggressors; when crossing is unavoidable, do it orthogonally. Sense lines longer than ~50 mm benefit from driven shields or continuous guard rings to bound capacitive pickup. Add 100–220 Ω series resistors at controller pins to damp ESD‑induced ringing without materially impacting noise.

USB and I2C interface constraints you must lock

USB 2.0 pairs at 90 Ω differential (±10%) with intra‑pair skew ≤1.25 mm keep the PHY happy and minimize emissions that leak into sensors. Place low‑capacitance TVS (junction <1 pF) at the connector. For I2C at 400 kHz, keep total bus capacitance <400 pF; 2.2–4.7 kΩ pull‑ups are typical. Route these away from the sensor region and avoid parallel runs with sense lines.

How to plan ESD return for 8 kV contact?

IEC 61000‑4‑2 8 kV contact events produce ~30 A first‑peak with ~0.7–1 ns rise. At ~1 nH/mm routing inductance, an extra 10 mm of return path can add ~300 V (V = L·di/dt) during the rise. Provide a short, explicit return to chassis: stitch ground/chassis vias every 2–3 mm along the bezel and around openings, and keep copper 0.25–0.5 mm back from edges to reduce surface flashover. Bond shield cans or frames with multiple vias directly to the return plane. Protect external interfaces with TVS at the connector; for sensor nets, prefer guard rings and 100–220 Ω series resistors over high‑C protectors that degrade SNR.

Stackup and overlay: numbers that predict sensitivity

On FR‑4 (εr ≈ 4), a practical 4‑layer is: L1 sensors and controller; L2 recessed keep‑plane (hatch or driven shield) set back 3–5 mm from the touch area; L3 power distribution; L4 bottom routing. Overlay capacitance follows C ≈ ε0·εr·A/d. Example: a 12 × 12 mm cell under 0.8 mm polycarbonate (εr ≈ 2.9) yields ≈4.6 pF; doubling overlay to 1.6 mm halves it to ≈2.3 pF. Include OCA thickness (50–200 µm) in d; lower‑εr adhesives reduce C further. Symmetric lamination (e.g., 7628 prepreg above/below core) limits warp that can change overlay gap.

Debug playbook: low sensitivity or jitter

Record baseline counts and touch SNR (target ≥10:1). Remove the overlay to separate electrical from mechanical causes. If you see 50/60 Hz hum or USB‑related tones in the spectrum, increase spacing to aggressors, convert a ground plane under the route to driven shield, or slow the scan rate per controller guidance. Moisture trapped under the overlay shifts the baseline; add vent paths and conformal coat around—but not over—the sensor area if needed.

Manufacturing notes for fab and bring‑up

State IPC acceptance class (Class 2 or Class 3) in the drawing, and include RoHS/REACH in the notes. Add impedance notes for USB (90 Ω diff) and any single‑ended controls. Tent or mask‑fill any vias under the overlay to avoid resin voids and overlay thickness variation. Provide explicit test points and ground loops near the sensor for probe‑based validation.