Capacitor discharge pulse driver PCB: what to review before fab?

Here is a rigorous review checklist and layout guidance to sign off a capacitor discharge pulse driver PCB before fabrication.

Define the pulse and stress budget

• Energy: E = 0.5·C·(Vstart² − Vend²). This sets device, snubber, and clamp sizing.

• Edge rate: di/dt ≈ V/Lloop. With 400 V and 20 nH, di/dt ≈ 20 kA/µs; gate/loop design must tame this.

• Repetition and thermal: RMS current for copper sizing uses duty: IRMS ≈ Ipk·√(tpulse/Trep).

• Spectral content: fedge ≈ 0.35/trise. A 50 ns edge has ~7 MHz content; layout is RF-like even if average frequency is low.

How much creepage and clearance do you need?

Use IPC-2221B external conductor clearance as a baseline: 301–500 V: 2.5 mm; 501–750 V: 3.2 mm; 751–1000 V: 4.0 mm. For polluted environments or long life, add ≥50% margin or follow IEC 60664-1 creepage rules by CTI/material group. Practical tips:

• Keep HV copper on one side with wide solder mask dams; add routed slots to extend creepage along surfaces.

• Avoid solder mask-only reliance for basic insulation; conformal coating helps but does not replace spacing.

• Pull low-voltage control away from HV copper by the same or greater distances; add guard copper connected to chassis where allowed.

Minimize loop inductance in the discharge path

• Use a compact, coaxial-like path: capacitor bank → switch → load → return plane directly under the forward path.

• Target Lloop < 10–30 nH for the high-current ring. Stitch the return with dense vias (pitch 1–2 mm around the switch and shunt).

• Kelvin source/emitter: route a separate, tight gate-return trace from the device source/emitter sense pin back to the driver.

• Short, wide copper for the main current: keep forward and return stacked (outer layer trace over solid inner plane) to reduce ESL.

Gate drive, CMTI, and false turn-on control

• Driver isolation CMTI: choose >100 kV/µs for high dV/dt nodes.

• Split gate resistors (Ron/Roff) to tune switching; typical di/dt targets are 0.5–2 kA/µs for TO‑247 and module devices.

• Add Miller clamp or negative turn-off bias (e.g., −2 to −5 V for IGBT) to prevent retrigger on fast dV/dt.

• Place TVS clamps on gate, tight to device pins; route the gate loop away from the power loop.

Copper width, vias, and thermal pulses

• Outer layers carry pulses; 2 oz (≈70 µm) with 8–12 mm width yields ~0.7–0.84 mm² cross‑section. R ≈ ρ·L/A ≈ 0.02–0.03 Ω/m; IRMS sets heating per IPC‑2152.

• Via current: plating area Avia ≈ tplating·π·Dhole. Example: 25 µm plating, 0.30 mm hole → Avia ≈ 0.0236 mm²; R ≈ 1.1 mΩ for 1.6 mm board. Parallel 10–20 vias to cut L and I density at device leads and shunt ends.

• Keep via barrels short; if board is thick, use back‑to‑back vias with surface copper to avoid long inductive stubs.

Snubbers, clamps, and EMI containment

• RC snubber across the switch to damp Lloop; start with Csnub ≈ 2–5× Lloop/Rload² and tune by ring‑down.

• RCD or TVS clamps from switch node to bus limit overshoot to <10% of bus voltage.

• Place snubber parts adjacent to device pins; keep their loop area as small as the main loop.

• Add common‑mode capacitors from switch node to chassis (Y‑cap values in the nF range) only if safety allows; verify leakage.

How do you measure current and voltage safely?

• Shunt: 0.2–0.5 mΩ gives 20–50 mV at 100 A; amplifier bandwidth >5–10× 1/trise (e.g., >100 MHz for 10 ns edges, >10 MHz for 100 ns).

• Rogowski or coaxial current probe for nonintrusive pulse shape.

• Differential HV probe with adequate bandwidth; minimize loop in measurement leads.

• Add coax outputs (SMA) for node sensing with series damping (22–51 Ω) to protect instruments.

Bring-up and protection checklist

• Precharge or series start‑up resistor to limit inrush; verified bleed path (time constant documented on silkscreen).

• Desat or overcurrent shut‑down in the driver with blanking; UVLO enforced.

• Interlocks and HV present indicator; discharge test point with safe spacing and clear labels.

• First shots at reduced V and with a ballast resistor; record di/dt, overshoot, and case temperature.

Fabrication notes and acceptances

• 4‑layer stackup works well: L1 power, L2 solid return, L3 control routing, L4 chassis/HV guard. Keep control on inner layers away from switch node.

• Specify solder mask expansion to maintain creepage; add routed slots or keep‑outs between HV and LV nets.

• Choose finish per current interface: HAL for thick copper contact pads; ENIG for fine control circuitry.

• Document IPC acceptance: Class 2 for general; Class 3 if mission‑critical. RoHS/REACH material control if required.

• For documentation, include a table of required clearances/creepages by net class and target dI/dt limits in fab notes.

One-page DFM checklist for this PCB

• Net classes defined with IPC‑2221B clearances; creepage extended by slots where needed

• Discharge loop area minimized; return plane continuous under forward current

• Gate drive Kelvin routing; CMTI and Miller countermeasures specified

• Copper width and via arrays sized from IRMS and di/dt; thermal rise checked per IPC‑2152

• Snubber/clamp physically tight to switch; EMI return to chassis controlled

• Measurement connectors and protection resistors placed; probe bandwidth considered

• Precharge/bleeder, interlocks, and labels present; test sequence documented

Quality, acceptance, and response

HyperPCB operates an ISO 9001:2015 certified QMS (SGS CN-2023-Q1156, valid to June 2027). Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria. RoHS and REACH compliance is supported for hazardous substance control. Quotes are returned within 24 hours and DFM feedback within 1 business day.