Controlled‑impedance PCB: verified formulas and worked stackup examples

A controlled‑impedance calculator maps geometry and material (h, εr, t, w, s, mask) to Z0 and Zdiff; for example, with εr = 3.6, h = 0.18 mm, t = 35 µm, w = 0.38 mm, no mask, Z0 ≈ 50 Ω; spacing s ≈ 0.45 mm yields Zdiff ≈ 100 Ω on an outer microstrip.

What does a controlled‑impedance calculator compute?

It returns single‑ended Z0 and coupled‑pair impedances (odd/even, Zdiff) from geometry and dielectric constants. For external microstrip, the calculator uses effective permittivity εeff (air above, dielectric below); for inner stripline it uses bulk εr.

Formulas you can check directly:

• Microstrip (Hammerstad‑like εeff): εeff ≈ (εr+1)/2 + (εr−1)/2 · 1/√(1+12h/w)

• Microstrip Z0: Z0 ≈ (60/√εeff) · ln[8h/(w+t) + (w+t)/(4h)]

• Symmetric stripline (trace centered, plane spacing b): Z0 ≈ (60/√εr) · ln[1.9b/(0.8w + t)]

Microstrip example with numbers you can verify

Target: 50 Ω single‑ended on FR‑4‑class εr = 3.6, h = 0.18 mm, t = 35 µm, no solder mask.

• Compute εeff ≈ (3.6+1)/2 + (3.6−1)/2 · 1/√(1+12·0.18/0.38) ≈ 2.80

• Then Z0 ≈ (60/√2.80) · ln[8·0.18/(0.38+0.035) + (0.38+0.035)/(4·0.18)] ≈ 50.1 Ω at w ≈ 0.38 mm

Add a 25 µm solder mask (Dk ≈ 3.2) on top: a 2D stackup model typically drops Z0 by ≈ 1.5–2.5 Ω for this geometry. Shrinking the width to ≈ 0.36 mm restores ≈ 50 Ω with mask included. For a 100 Ω differential pair using the 0.38 mm microstrip, weak coupling (s ≈ 0.45–0.50 mm) brings Zdiff close to 2·Z0 ≈ 100 Ω; tighter spacing (s ≈ 0.24 mm) lands near 90 Ω for the same single‑ended geometry.

Stripline example: 85 Ω and 100 Ω targets

Symmetric stripline, εr = 3.6, plane‑to‑plane b = 0.20 mm, copper t = 18 µm.

• Solve 50 Ω single‑ended with Z0 ≈ (60/√3.6)·ln[1.9·0.20/(0.8w+0.018)] ⇒ w ≈ 0.075 mm

• 100 Ω diff: with w ≈ 0.075 mm, s ≈ 0.10–0.12 mm typically yields Zdiff ≈ 98–102 Ω

• 85–90 Ω diff: reducing spacing to s ≈ 0.05–0.08 mm strengthens coupling and drops Zdiff into the 85–90 Ω band

These ranges can be reproduced in a 2D solver by including the exact b, t, w, s, and εr above.

Which inputs move impedance the most, quantitatively?

• Height h dominates Z0 for microstrip because it sets w/h. With h = 0.18 → 0.20 mm (+11%) at fixed w = 0.38 mm and t = 35 µm, Z0 rises by roughly 3 Ω; widening w ≈ 0.02–0.03 mm compensates back to ≈ 50 Ω.

• Solder mask on microstrip (25 µm, Dk ≈ 3.2) typically lowers Z0 by ≈ 1.5–2.5 Ω at 50 Ω. Narrowing w by ≈ 0.02 mm recovers the target.

• Copper thickness: doubling outer copper from 35 µm to 70 µm reduces Z0 by ≈ 1–2 Ω at the same w due to increased effective width; trimming w by ≈ 0.02–0.03 mm offsets the change.

Do closed‑form equations hold at 10–28 Gb/s?

Closed‑form microstrip/stripline equations are frequency‑independent and ignore copper roughness and mask loading. A practical check using the microstrip case above:

• Baseline (no mask, no roughness): formula gives Z0 ≈ 50.1 Ω.

• Add a 25 µm mask (Dk 3.0–3.3) in a 2D solver: Z0 commonly falls to ≈ 48.0–48.8 Ω for this geometry.

• Enable a roughness model with RMS ≈ 1–2 µm: Z0 shift is usually < 1 Ω, but insertion loss increases noticeably in the 10–14 GHz Nyquist band (28 Gb/s signaling).

Actionable rule: include mask thickness and a reasonable roughness parameter in the solver; if the solver vs. equation delta exceeds ≈ 2 Ω, retune w or s and lock the mask in the stackup notes.

From calculator to fab notes and measurement

Call out laminate family, glass style, and finished foil weight on the drawing. Specify which nets are controlled impedance and their tolerance (±10% is a common starting point; tighten only if the interface spec demands it). Request impedance coupons on the same layers as the routed nets and ask the fabricator to provide TDR plots with target vs. measured widths so you can correlate CAM compensation with your model.

Manufacturing and compliance at HyperPCB

• Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria

• RoHS and REACH compliance is supported for hazardous substance control

• ISO 9001:2015 certified QMS (certificate CN-2023-Q1156, issued by SGS, valid until June 2027)

• Quotes are returned within 24 hours and DFM feedback within 1 business day

Typical interface targets to cross‑check

Ethernet/LVDS/HDMI/SATA: 100 Ω diff. USB 2.0 HS: 90 Ω diff. USB 3.x/PCIe: 85 Ω diff. Many RF/clock nets: 50 Ω single‑ended. Confirm the current spec revision before freezing the stackup.