Decoupling capacitors and power planes: how to hit PDN target impedance

Use tightly spaced power–ground planes and short‑loop MLCCs at each IC supply pin to keep PDN impedance below your target across frequency.

What actually provides decoupling?

Decoupling is a local energy source plus a low‑inductance path. MLCCs supply charge for fast di/dt, while the power–ground plane pair supplies mid‑ to high‑frequency capacitance with low spreading inductance. The IC’s package and die add on‑die/package capacitance at very high frequencies.

How do I set target impedance?

Set Ztarget = ΔV/ΔI. Example: 1.0 V rail, 5% ripple, 0.5 A step → Ztarget = 0.05/0.5 = 0.1 Ω. Your PDN (VRM + bulk + MLCCs + planes + vias + IC package) should stay below this magnitude across the rail’s spectral content (from VRM crossover up to IC edge rates).

Which capacitor values and packages actually help?

• Bulk (10–100 µF, e.g., tantalum/polymer) shapes <100 kHz–1 MHz.

• Mid band (0.47–2.2 µF MLCC) covers ~1–20 MHz.

• High band (10–100 nF MLCC, 0402 or 0201) covers >50–100 MHz.

ESL dominates at high f. Typical mounting ESL: 0402 ≈ 0.2–0.4 nH, 0603 ≈ 0.5–0.8 nH. A single 1 nH path is 0.63 Ω at 100 MHz (XL = 2πfL), already above many Ztargets. That’s why package size and mounting matter as much as value.

How close is close enough for placement?

Keep the loop area from IC supply pin → cap → planes as small as possible. Same‑side placement, routing direct to planes, and via‑in‑pad (or two short vias per pad) typically beats opposite‑side placement through a long via pair. As a rule of thumb, keep total interconnect length from IC pin to cap pad under ~1–2 mm for high‑speed logic rails and under BGAs place 0402/0201 MLCCs in‑field with microvias where available.

Power–ground plane pairs as capacitors

Treat the plane pair like a distributed capacitor with low ESR/ESL. Capacitance per area C ≈ εrε0·A/d. For FR‑4 (εr ≈ 4.2) at 0.10 mm spacing, C ≈ 240 pF/in². Doubling spacing to 0.20 mm halves it to ≈120 pF/in². Plane‑pair inductance per square is ≈ μ0·h; at 0.10 mm it’s ~126 pH/square, aiding high‑frequency current spreading. Tighter spacing (e.g., 3–4 mil, ~75–100 µm) materially lowers PDN impedance.

Why do mixed values create anti‑resonance peaks?

Parallel caps with different ESL/ESR form resonant tanks that spike impedance between their self‑resonances. Mitigate by: keeping mounting inductance very low; using several identical values in parallel instead of many different values; adding intentional damping (caps with modest ESR or a small series resistor in noncritical rails); and relying on plane‑pair capacitance at the highest band.

Via strategy and return current

Each via adds ~0.25–0.5 nH depending on length and diameter. A via pair can be ~0.5–1 nH. Use two vias per capacitor pad where space allows, or via‑in‑pad microvias down to the nearest plane pair. Stitch ground vias around ICs and near plane transitions so return current has short paths and minimal loop expansion across splits or layer changes.

Stackup choices that help the PDN

Place at least one tight power–ground pair adjacent to the IC routing layer. Examples: use a 0.10 mm (≈4 mil) dielectric (e.g., 2116 prepreg) between a power and ground plane for high‑speed rails; 0.05–0.08 mm (106/1080 styles) where fabrication allows for very fast edges. Avoid slicing the reference planes under critical ICs; keep rails contiguous, and route high di/dt currents over solid returns.

Practical numbers you can use

• Start with 0.1 µF (0402) per VDD pin group, plus 1 µF per IC rail, then size up from Ztarget.

• Keep cap‑to‑pin loop length ≤1–2 mm for fast digital rails; ≤5 mm for slower analog rails.

• Two vias per pad cut mounting inductance noticeably vs one; via‑in‑pad is better.

• Check SRF: ensure each MLCC’s self‑resonant frequency sits within a useful band for your rail’s spectrum.

• Plane spacing 0.10 mm yields ≈240 pF/in²; 0.05 mm ≈480 pF/in² (FR‑4). Use this to estimate high‑f decoupling from the stackup.

• Validate Z(f) with a shunt‑through or 1‑port VNA method on a test coupon or the assembled board.

How to verify the PDN quickly

Model the rail’s impedance (VRM + bulk + MLCC network + plane pair) and compare to Ztarget. Then spot‑check with a VNA: a 2‑port shunt‑through fixture gives good accuracy from a few hundred kHz to hundreds of MHz. On the bench, also measure transient droop on the rail with a low‑inductance probe during current steps.

Manufacturing notes for reliable decoupling

Choose MLCCs with stable dielectrics (X7R for logic rails) and de‑rate voltage to limit DC bias loss. Specify controlled dielectric thickness between your power–ground pair; note that common FR‑4 prepregs (e.g., 2116 ≈0.10 mm, 7628 ≈0.18 mm) directly change plane‑pair capacitance and inductance. Keep solder mask openings tight around 0201/0402 to minimize mounting stray inductance.

What HyperPCB can build for this kind of PDN

• ISO 9001:2015 certified QMS (certificate CN-2023-Q1156 by SGS, valid to June 2027) [1]

• Quotes within 24 hours and DFM feedback within 1 business day to vet your stackup and PDN geometry [2]

• Boards built and inspected to IPC Class 2 or Class 3 acceptance criteria [5]

• RoHS and REACH compliance supported for hazardous substance control [6]

• Partner factory AEGIS holds ISO 9001:2015, ISO 14001:2015, ISO 45001:2018 [3] and ISO 13485:2016, IATF 16949 [4]

• Partner factory manufactures its own high‑frequency laminates and supplies RF PCB fabricators in China, including publicly listed PCB companies [7]

Bottom line

Hit your Ztarget by combining low‑ESL MLCCs placed within millimeters of pins with a tightly spaced power–ground plane pair, then verify with measurement. The stackup choice is as decisive as the capacitor list.