Do you need your fab's stackup for controlled‑impedance PCBs?

You don’t need JLCPCB’s exact standard stackup to achieve controlled impedance; define target impedances and dielectric constraints, and your fabricator will tune trace widths and gaps to hit them.

What does “controlled impedance” actually control?

Controlled impedance means the single‑ended (Z0) and differential (Zdiff) impedance of specific traces are constrained by the stackup and geometry. Z is set by dielectric thickness (H), dielectric constant (Dk vs frequency), copper thickness (t), trace width (W), spacing (S), and reference plane continuity. Typical targets: 50 Ω single‑ended, 90 Ω differential (USB/HDMI), 100 Ω differential (Ethernet), 85 Ω differential (PCIe/SATA). Outer layers are microstrip; inner layers with planes on both sides are stripline. First‑order values can be estimated with IPC‑2141A; final values should be field‑solved by the fabricator.

Example 4‑layer stackup that meets 50 Ω and 90 Ω

A practical FR‑4 buildup for outer‑layer impedance:

• Material: FR‑4, Dk ≈ 3.7–3.9 at 1 GHz, Df ≈ 0.01–0.02

• Copper: outer 0.5 oz (≈17 µm finished), inner 1 oz (≈35 µm)

• L1–L2 dielectric ≈ 0.10 mm (e.g., two plies 1080 prepreg)

• L2: solid GND plane

• Core (L2–L3) ≈ 0.36 mm; L3: PWR or solid plane; L4: signal

With H(L1‑to‑L2) ≈ 0.10 mm and t ≈ 17 µm:

• 50 Ω microstrip on L1: W ≈ 0.18–0.22 mm (7–9 mil)

• 90 Ω differential on L1: two 50 Ω lines, W ≈ 0.20 mm with S(edge‑to‑edge) ≈ 0.20–0.25 mm (8–10 mil)

Final widths vary with actual resin content and copper roughness; your fab will solve exact values.

Example 6‑layer stackup for 85 Ω and 100 Ω differential

A symmetric FR‑4 buildup that supports inner‑layer striplines:

• Copper: 0.5 oz (≈17 µm) on all layers

• Dielectrics (approximate pressed thickness): L1–L2 ≈ 0.10 mm; L2–L3 ≈ 0.18–0.20 mm; L3–L4 ≈ 0.18–0.20 mm; L4–L5 ≈ 0.18–0.20 mm; L5–L6 ≈ 0.10 mm

• L2 and L5: planes (GND/PWR as needed)

Results with Dk ≈ 3.7–3.9:

• 50 Ω microstrip on L1: W ≈ 0.18–0.22 mm (7–9 mil)

• 85 Ω differential symmetric stripline on L3 or L4: W ≈ 0.10–0.12 mm (4–5 mil), S(edge‑to‑edge) ≈ 0.14–0.18 mm (6–7 mil)

• 100 Ω differential symmetric stripline: keep W ≈ 0.10–0.12 mm, increase S(edge‑to‑edge) ≈ 0.20–0.24 mm (8–10 mil)

These are ballpark; your fabricator’s field solver will set production values.

Do I have to copy JLCPCB’s exact materials?

No. If you’re matching a previous JLCPCB build, share their published dielectric thicknesses, Dk assumptions, and copper weights. Another shop can meet the same impedances by adjusting W/S a small amount (often ~0.1–0.25 mm shift in width or gap) to account for different resin contents or copper roughness. The key is consistent plane referencing and documented targets.

What to send the fabricator for impedance sign‑off

• Target Z: e.g., 50 Ω SE on L1 (microstrip), 90 Ω diff on L1, 85 Ω diff on L3 (stripline)

• Stack diagram: layer order, plane assignment, dielectric thicknesses (mm) and material family (e.g., 1080/2116/7628)

• Copper thickness per layer (finished µm or oz)

• Preferred min/typ trace width and spacing constraints

• Frequency of interest for Dk/Df (e.g., 1–5 GHz)

• Surface finish (e.g., ENIG, HASL) if relevant to outer‑layer roughness

• Required impedance tolerance (±10% is common) and coupon test method/location

• Any pair‑routing rules (skew, length match, reference continuity)

Tolerances, copper roughness, and glass weave

Impedance tolerance of ±10% is typical unless otherwise agreed. Rougher copper (larger RMS) increases effective Dk and lowers Z by a few percent; specifying low‑roughness/HVLP copper helps at multi‑GHz. Glass styles affect skew: 7628 can introduce tens of ps skew on long pairs; mitigations include spread‑weave laminates, routing pairs at 7–15° to the weave, or mixing prepregs (e.g., 1080/2116) adjacent to critical layers.

Standards and test coupons

Use IPC‑2141/2141A for preliminary sizing and request the fabricator’s 2.5D field‑solver results for sign‑off. Impedance acceptance typically follows IPC‑6012 with on‑panel coupons that mirror your critical layers (same H, copper, W/S) and are measured at the intended frequency.

HyperPCB quoting and DFM support

HyperPCB operates under an ISO 9001:2015 certified quality management system (certificate no. CN-2023-Q1156, issued by SGS, valid until June 2027). We return quotes within 24 hours and DFM feedback within 1 business day, so you can lock stackups and impedances before layout risk accumulates.