Edge Cut Error with Horizontal (Edge‑Mount) SMA in KiCad/Altium: Causes and Fixes

Yes—edge cut errors with a horizontal (edge‑mount) SMA usually mean your footprint or copper is violating the board outline or copper‑to‑edge rules in your CAD tool.

Why do edge cut errors appear with horizontal SMA?

A right‑angle/edge‑mount SMA expects the board edge to be a precise reference. Many footprints include a “board edge” line inside the footprint, or place copper right up to the edge for the launch. CAD DRC then flags: duplicated outlines, open or intersecting Edge.Cuts/Board Shape, or copper too close to the routed edge. The fix is to keep the real outline singular and closed, and apply local rules where the launch must meet the edge.

What triggers DRC in KiCad and Altium?

• KiCad: Extra Edge.Cuts segments inside the SMA footprint; non‑closed outline; overlapping edge segments; copper within the global Copper‑to‑Edge clearance (e.g., 0.25–0.5 mm typical) near the launch; holes/slots too close to edge

• Altium: Mechanical layer lines mistaken for board shape; multiple Board Shapes; Hole‑to‑Edge or Solder Mask‑to‑Edge rule violations at the ground tabs; pads extending beyond Board Shape

KiCad setup that avoids Edge.Cuts errors

Use only one closed outline on Edge.Cuts. If your SMA footprint includes any Edge.Cuts graphics as a placement aid, edit the footprint to move those lines to Dwgs.User so they are not treated as a second outline. In Board Setup > Design Rules > Constraints, set Copper to Edge Clearance to a value your fabricator accepts (0.25–0.50 mm is a common range for routed edges). For the SMA launch where copper must meet the edge, define a local Rule Area that sets Copper to Edge = 0.00 mm only in that small region. Keep NPTH tab holes at least 0.30–0.50 mm from the routed edge to avoid breakout unless the connector datasheet specifies closer. Ensure the outline is a single, non‑self‑intersecting polyline—no gaps or duplicates.

Altium setup for edge‑mount SMA without board shape errors

Define the Board Shape once (Design > Board Shape > Define from selected objects, or by outline import). Remove any board‑edge graphics embedded in the SMA footprint from contributing to Board Shape; keep them on a Mechanical layer for reference only. Set Rules: Clearance > Clearance (pad/track to Board Outline), Manufacturing > Hole To Board Edge Clearance, and Solder Mask Expansion. Use a Room or specific Clearance rule to allow 0.00 mm copper‑to‑edge only at the launch pads while keeping 0.25–0.50 mm elsewhere. If the footprint uses slots for ground tabs, define them as routed slots on the drill table and maintain adequate edge spacing to prevent breakout.

Copper‑to‑edge and mask numbers that generally work

For most routed outlines, 0.25–0.50 mm (10–20 mil) copper‑to‑edge is a practical global rule. V‑score typically needs more; many fabs want ≥0.40 mm. At the RF launch, the signal and side ground lands often need to be flush with the board edge; use a local exception (0.00 mm) only in that launch window. Open solder mask over the launch and connector ground pads; use 0.10–0.15 mm mask expansion around those pads to avoid mask slivers, and pull back mask from the literal routed edge by ~0.10 mm to reduce chipping.

Does board thickness matter for the horizontal SMA?

Yes. Many edge‑mount SMA connectors are designed for 1.57 mm (0.062 in) boards; vendors also offer 0.8/1.0/1.2 mm variants. Match the connector to your finished thickness including copper and plating. If your stackup uses thick outer copper (e.g., 2 oz), confirm the connector clamp area clears the extra height.

50 Ω launch geometry checklist

Target a 50 Ω microstrip into the edge: on 1.6 mm FR‑4 (Er ≈ 4.2), the microstrip width is commonly around 3.0 mm ±0.2 mm; confirm with your field solver using your actual stackup and mask. Keep a via fence tying top ground to the main ground plane along the launch—1.0 mm pitch is a common starting point with 0.30 mm drill and ~0.60 mm pad, placed about 0.5–0.7 mm from the trace edge. Maintain a short, straight launch; avoid solder mask between the connector’s ground jaws and the copper it clamps to.

How to diagnose which object causes the error fast?

In KiCad, hide all layers except Edge.Cuts and run Inspect > Design Rules Checker; look for overlapping or tiny edge fragments near the SMA. Then show F.Cu/GND layers and use the “Highlight Collisions” feature while hovering at the edge. In Altium, View Configuration > View Options > Board Shape allows you to visualize the active outline; then use PCB Rules And Violations to filter violations around the connector component to see which rule is tripping first.

Why this matters for fabrication

DFM will flag copper breaking out of the edge, mask too close to the route, or slots kissing the outline. Cleaning these before release reduces edge burrs and impedance drift at the RF launch, and prevents delays from CAM queries.

What we check on our side

We can return quotes within 24 hours and DFM feedback within 1 business day. We build and inspect to IPC Class 2 or IPC Class 3 acceptance criteria on request, and support RoHS and REACH compliance. Our ISO 9001:2015 certified quality management system (certificate no. CN-2023-Q1156, issued by SGS, valid until June 2027) governs document control and product realization. For RF work, note that our partner factory manufactures its own high‑frequency laminates and supplies RF PCB fabricators in China, including publicly listed PCB companies.

Release checklist to avoid the edge cut error recurring

Ensure the board outline is single and closed; keep any footprint “edge guides” off Edge.Cuts/Board Shape; apply local 0.00 mm copper‑to‑edge only at the SMA launch; verify hole/slot‑to‑edge spacing; and include a cross‑section drawing with finished thickness for the connector.