ESP32‑S3‑Mini‑1 software I2C not working? Root‑cause checklist

Software I2C on ESP32‑S3‑Mini‑1 usually fails from weak pull‑ups, unsuitable GPIOs, or RTOS timing; fix those and it works reliably.

Minimal wiring and pull‑ups

Use external pull‑ups to 3.3 V on SDA and SCL. Start with 4.7 kΩ at 100 kHz; for 400 kHz use 2.2–3.3 kΩ depending on bus capacitance. The internal pull‑ups on ESP32‑S3 are ~tens of kΩ and are too weak: with 45 kΩ and 100 pF, rise time tr ≈ 0.8473·R·C ≈ 3.8 µs, which violates I2C (1.0 µs max for Standard‑mode, 0.3 µs for Fast‑mode). Calculate Rp from your layout: Rp_max = tr_max/(0.8473·Cbus). Example: Cbus = 200 pF, Fast‑mode tr_max = 300 ns → Rp ≤ ~1.8 kΩ. Also respect sink current: Rp_min ≈ VDD/IOL; at 3.3 V, IOL = 3 mA (Fast‑mode), Rp ≥ ~1.1 kΩ. Keep grounds common and leads short; confirm idle high = 3.3 V.

Which GPIOs can I use for bit‑banged I2C?

Pick two fully capable GPIOs that aren’t used by boot strapping, USB, flash/PSRAM, or other peripherals (check your module’s pinout). Configure them as open‑drain outputs and inputs (never drive logic high; let the pull‑up do that). If you must test quickly, move to the hardware I2C controller first (any routable GPIO pair on ESP32‑S3 works) to confirm wiring and pull‑ups; then return to software I2C.

Timing, FreeRTOS, and clock stretching

Bit‑banging is sensitive to preemption. Run the transaction in a critical section or disable interrupts briefly around the bit‑banged edges to stabilize SCL high/low periods. Start at 50–100 kHz. Implement clock‑stretch handling: after releasing SCL high, sample SCL and wait until the line is actually high before proceeding; some slaves hold SCL low while processing. If your software master ignores this, reads/writes will hang.

Scope checks that prove the point

Measure tr and tf on SDA/SCL. For Standard‑mode, tr ≤ 1000 ns; for Fast‑mode, tr ≤ 300 ns. Low‑level VIL should stay below ~0.3·VDD (≈1.0 V at 3.3 V). If a line is stuck low, the slave may be mid‑byte—toggle SCL ~9 times with SDA released, then issue a STOP. If edges ring, add 22–33 Ω series resistors near the master and place pull‑ups near the ESP32‑S3.

PCB layout notes for stable I2C

Keep SDA/SCL short and parallel only over a solid ground; avoid long stubs and reduce via count. Budget Cbus (device pin + trace + connector) under ~100–200 pF for 100–400 kHz. Use a single‑point pull‑up location near the master. Separate from fast edges (clocks, USB) and give a clear return path to limit crosstalk.

Troubleshooting checklist

• Confirm 2.2–4.7 kΩ pull‑ups to 3.3 V; measure idle high = 3.3 V.

• Try hardware I2C (e.g., Wire.begin(sda, scl, 100000) or ESP‑IDF i2c_driver_install). If this works, your issue is software timing.

• Move to different GPIOs not used at boot/USB/flash; verify with a simple loop that the pins can toggle and read back.

• Reduce bit‑bang speed and add precise delays; guard the bit‑bang with a critical section to avoid jitter from task switches.

• Implement clock‑stretch wait on SCL; bail out with a timeout if SCL stays low.

• If a device can be 5 V, ensure the pull‑ups are to 3.3 V or use a proper level shifter; do not pull up ESP32 lines to 5 V.

• Bus stuck low? Send 9 SCL pulses with SDA released, then STOP, then re‑init.

Manufacturability and compliance notes

If I2C is flaky only on assembled boards, check solder (open pull‑ups) and parasitics from long runs/connectors. We build to IPC Class 2 or Class 3 acceptance criteria and support RoHS/REACH for hazardous substances. Our QMS is ISO 9001:2015 certified (SGS CN-2023-Q1156, valid to June 2027). Quotes are returned within 24 hours and DFM feedback within 1 business day.