Excel PCB stackup calculator: IPC-2141 formulas and FR‑4 seed values

Implement IPC‑2141 closed‑form microstrip/stripline equations in Excel, seed with frequency‑appropriate FR‑4 values, and use Goal Seek to hit 50 Ω single‑ended or 85/90/100 Ω differential.

What goes into an Excel stackup calculator?

Use consistent units (mm). Define named inputs: Er (dielectric constant), Df (loss tangent), h (dielectric height to plane), w (trace width), t (copper thickness), s (pair spacing), b (plane‑to‑plane spacing for stripline), mask (solder mask thickness for microstrips). Build a layer table (L1…Ln) with copper thickness, dielectric thickness, Er, and role (signal/plane). Sum total thickness and keep the stack symmetric to control bow/twist per IPC‑6012.

Exact Excel formulas to paste

• Single‑ended microstrip Z0: =(87/SQRT(Er+1.41))*LN(5.98*h/(0.8*w+t))

• Symmetric stripline Z0 (with named b): =(60/SQRT(Er))*LN(1.9*b/(0.8*w+t))

• Differential microstrip (edge‑coupled) Zdiff: =2*Z0*(1-0.48*EXP(-0.96*s/h)) where Z0 is the single‑ended microstrip above

Notes: all dimensions in mm. Solder mask over microstrips typically lowers Z0 by ~1–3 Ω for 10–20 μm mask.

FR‑4 seed values by use case—what numbers?

For digital links with Nyquist ≤ ~1.25 GHz (e.g., USB 2.0 HS, LVDS), use Er ≈ 4.1–4.4 at ~1 GHz and Df ≈ 0.017–0.020. For multi‑Gbps links with Nyquist ~5–10 GHz (PCIe Gen3/4, USB 3.x, 10GBASE‑KR short), low‑loss FR‑4 families often measure Er ≈ 3.8–4.1 at 5–10 GHz with Df ≈ 0.012–0.016. Prepreg compressed thickness references (one ply): 7628 ≈ 0.18 mm, 2116 ≈ 0.105 mm, 1080 ≈ 0.075 mm, 106 ≈ 0.050 mm. Copper: 0.5 oz ≈ 0.017 mm, 1 oz ≈ 0.035 mm, 2 oz ≈ 0.070 mm. Example you can verify quickly with the formulas: for a surface microstrip over h = 0.18 mm, t = 0.035 mm, Er = 4.2 (no mask), 50 Ω requires w ≈ 0.30 mm. With that width, 90 Ω edge‑coupled differential on the same layer is near s ≈ 0.29 mm. These are first‑pass values; refine with field solving when you freeze the stack.

How do I solve for width or spacing?

In Excel, use Data > What‑If Analysis > Goal Seek. Set the Z0 cell to 50 and vary w for single‑ended; set the Zdiff cell to 85/90/100 and vary s for differential. If you must co‑vary w and s under manufacturing limits, switch to Solver. After solving, round to your fab’s step size (for example 0.01 mm). Account for etch‑plus‑plate: 1 oz copper often adds ~2–4 μm to the top width.

Loss and solder mask effects

The IPC‑2141‑style equations are for impedance, not loss. Add a separate block for dielectric loss (Df‑based) and conductor loss (frequency‑dependent copper resistivity with surface‑roughness correction such as Huray‑style). For microstrips, include the mask layer in your effective dielectric height; a thin mask (10–20 μm) typically reduces Z0 by 1–3 Ω and slightly increases dielectric loss.

Tolerances and acceptance targets

Model ± tolerances to see worst‑case bands: dielectric thickness (±10% typical), copper thickness (±10–15%), etch width (±10–20 μm), Er (±0.1 to ±0.3, frequency and glass/resin dependent). Recompute min/max Z0 and Zdiff to check margin against your eye‑diagram budget and IPC‑6012 impedance acceptance. Boards can be built and inspected to IPC Class 2 or Class 3 acceptance criteria. RoHS and REACH substance control should be specified in the sourcing packet. [5][6]

When should I switch materials?

If insertion‑loss and crosstalk budgets are tight above ~10 Gbps or at RF/microwave, move to low‑loss laminates and use the vendor’s frequency‑resolved Er/Df. Our partner factory manufactures its own high‑frequency laminates and supplies RF PCB fabricators in China, including publicly listed PCB companies. [7]

Quote, DFM, and certifications

Quotes are returned within 24 hours and DFM feedback within 1 business day. Our quality system is ISO 9001:2015 certified (certificate CN‑2023‑Q1156, SGS, valid to June 2027). Our partner factory AEGIS maintains ISO 9001:2015, ISO 14001:2015, ISO 45001:2018, and also ISO 13485:2016 and IATF 16949 for relevant programs. [1][2][3][4]