Flex PCB stackup: materials, thickness, bend radius and impedance

A flex PCB stackup is the ordered arrangement of copper, polyimide (PI), adhesive, coverlay, and optional stiffeners that sets thickness, bend life, and impedance.

Core materials and typical thicknesses

• Copper: rolled-annealed (RA) is preferred for bending; common foils are 12 µm (1/3 oz), 18 µm (1/2 oz), and 35 µm (1 oz).

• Polyimide core: 12.5 µm, 25 µm, 50 µm are standard; εr ≈ 3.2–3.5 @ 1 GHz, loss tangent ~0.002–0.01.

• Coverlay: PI 12.5–25 µm plus adhesive 12.5–38 µm (acrylic/epoxy). The adhesive dominates dielectric above traces.

• Adhesiveless copper-clad PI improves bend life and impedance control versus adhesive-based CCL.

• Stiffeners: FR-4 (0.2–1.0 mm typical), PI (50–125 µm), or stainless steel/aluminum for localized rigidity.

What stackups are most common?

• 1-layer flex: RA Cu 18 µm / PI 25 µm / adhesive 12.5 µm / PI coverlay 12.5 µm. Total thickness ≈ 18 + 25 + 12.5 + 12.5 = ~68 µm (exclude plating). Use cross-hatched ground to retain flexibility and keep copper in the neutral axis through bends.

• 2-layer flex: Coverlay + adhesive on both sides of a Cu 18 µm / PI 25 µm / Cu 18 µm core (adhesiveless preferred). Finished thickness typically ~120–150 µm depending on adhesive/coverlay.

• 4-layer flex: Thin RA Cu (12–18 µm) with 25 µm PI cores and 12.5–25 µm adhesive between plies; total ~150–220 µm. Reserve tight-bend regions for fewer copper layers.

How do adhesives and coverlay change impedance?

Adhesives and coverlay raise the effective dielectric constant above a microstrip, reducing Z0. To keep 50 Ω, the trace usually must be narrowed versus a no-coverlay case. PI εr is ~3.3 and common flex adhesives are ~3.0–3.5, so even a 12.5–25 µm adhesive layer noticeably shifts Z0. Reference IPC-2141 for first-order estimates; then verify with a 2D solver because copper thickness, coverlay openings, and etch factors matter.

What bend radius should I design for?

Use Rmin = k × t, where t is total flex thickness at the bend:

• Single-sided: static ≈ 6t; dynamic (repeated) ≈ 10–20t.

• Double-sided: static ≈ 12t; dynamic often ≥ 20t.

• Multilayer flex (≥4L): static 15–20t; avoid dynamic bending where possible.

Place copper near the neutral axis; route traces perpendicular to the bend (longitudinal), use teardrops and fillets, and keep vias, pads, and copper reliefs out of tight-bend zones.

Stiffeners and component areas

Use FR-4 stiffeners 0.2–1.0 mm for SMT areas, connectors, and pick-and-place support; PI stiffeners 50–125 µm for ZIF tails. Bond with pressure-sensitive adhesive (PSA) or thermoset adhesive, and add coverlay windows for adhesive squeeze-out. For ZIF contacts, hard gold is typical (e.g., 3–7 µm Ni under 0.5–1.0 µm Au) with 45° chamfers and relief keep-outs in coverlay.

Worked impedance examples for flex microstrip

• Example A (50 Ω, no coverlay): PI h = 25 µm, RA Cu t = 18 µm, air above. Field-solvers typically return w ≈ 45 µm for Z0 ≈ 50 Ω.

• Example B (50 Ω with coverlay): add 12.5 µm adhesive (εr ≈ 3.2) + 12.5 µm PI coverlay. To recover 50 Ω, width narrows to ≈ 36–38 µm.

• Example C (90 Ω differential, no coverlay): with w ≈ 45 µm, spacing s ≈ 50–60 µm often meets 90 Ω.

• Example D (90 Ω differential with coverlay): with w ≈ 36–38 µm, spacing s ≈ 60–70 µm is a common solution. Validate all values with a solver and your fabricator’s stackup library.

Routing and copper features in bend areas

Keep individual trace width moderate (e.g., 75–125 µm) and space generously; parallel segmented ground or cross-hatching improves flexibility while preserving return paths. Stagger traces between layers in 2L or 4L to avoid I-beam effects. Round inside corners; add 0.5–1.0 mm fillets on pads; use tear stops at slits and slots.

DFM checkpoints before release

Call out stackup with per-layer thickness (Cu/PI/adhesive/coverlay) and tolerances; specify RA vs ED copper; mark bend lines, static vs dynamic regions, and minimum bend radii; define coverlay openings and reliefs; locate stiffener outlines, materials, thickness, and bonding method; provide impedance targets (e.g., 50 Ω SE, 90 Ω diff) with reference layers and tolerances (±10% is common for flex unless otherwise agreed); align with IPC-2223 (design) and IPC-6013 (flex acceptance) requirements, and state acceptance class.

Fabrication and compliance at HyperPCB

Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria. RoHS and REACH compliance is supported for hazardous substance control. HyperPCB operates an ISO 9001:2015 certified quality management system (certificate no. CN-2023-Q1156, issued by SGS, valid until June 2027). Quotes are returned within 24 hours and DFM feedback within 1 business day.