Gate‑driver package and pinout: concrete PCB rules and numbers

Pick QFN/LGA for fast edges and wide‑body SOIC for isolation; route each gate output with its return as a Kelvin pair to minimize loop inductance.

Package choice changes inductance and creepage

Lead‑framed SOIC (8/14/16) carries roughly 1–2 nH per lead. Narrow‑body SOIC‑16 yields about 3.9 mm creepage, while wide‑body SOIC‑16 adds around 8 mm creepage for reinforced isolation. QFN/DFN with exposed pads cut package parasitics below about 0.5–1 nH and improve thermal conduction. LGA/chip‑scale packages reduce loop inductance further (<0.2–0.5 nH path contributions) and suit fast GaN/SiC edges with high dv/dt. Driver modules integrate isolation and a DC/DC stage; lay them out with a physical split between primary and secondary copper and keep slots/keepouts under the barrier to preserve creepage.

How tight must the HO–HS loop be?

Voltage developed on the gate loop is VL = Lloop × di/dt. If your turn‑on current step is 5 A in 10 ns (0.5 A/ns) and you want VL ≤ 1.5 V to protect a 5–6 V GaN gate, Lloop must be ≤ 3 nH. A single through‑via (≈0.5–1 nH for a 0.3 mm drill through 1.6 mm FR‑4) plus a SOIC lead (≈1–2 nH) already consumes most of that budget; QFN/LGA and duplicate OUT/COM pins materially help. For SiC/MOSFET with 10–15 V drive, budgeting VL ≤ 3 V is typical; with 1 A/ns edges that implies Lloop ≤ 3 nH. Keep the HO–HS (or OUT–COM) current path compact, use parallel routes for gate and return, and use all duplicated output/return pins with multiple vias at the device pads.

Pin groups to treat as Kelvin pairs

• HO–HS (high‑side drive and switch node return), OUT/LO–COM (low‑side drive and source return), VB–VS (bootstrap supply and return), VDD–GND (logic/driver core), DESAT–COM (sense and quiet return). Place the local 100 nF X7R decoupler directly across each pair; keep the loop length under a few millimetres, ideally ≤ 2–3 mm between pins and capacitor lands.

Bootstrap sizing with a worked example

Size CBOOT for all charge taken each on‑time: CBOOT ≥ (Qg@VGS + IHB × ton + margin)/ΔV. Example: Qg = 30 nC at 12 V, IHB (high‑side bias current) = 1 mA, fSW = 100 kHz, D = 0.5 → ton = 5 µs. With ΔV = 0.5 V and a 10–20% margin for leakage/ESR, CBOOT ≥ (30 nC + 1 mA × 5 µs)/0.5 V = (30 nC + 5 nC)/0.5 V = 70 nF. Select 220 nF X7R (≥ 25 V rating) to cover tolerance and temperature drift. Place the diode and CBOOT tight to VB and HS/VS pins; do not return the bootstrap capacitor to a distant ground—its return is HS/VS.

Isolated grounds—what connects where?

Treat the secondary‑side COM/COM2 (or HS/VS on high‑side) as the Kelvin source for the power switch. Route OUT/HO to the gate and return it to COM/HS with a dedicated, local return; do not share this with power current. Maintain the datasheet’s creepage/clearance across the isolation barrier (wide‑body SOIC packages are commonly used for reinforced isolation at ~5 kVrms test with ~8 mm creepage). If the system requires a primary‑to‑secondary reference for EMC, implement it off‑driver (for example, at the power entry or star point), not through any driver pins or inner‑layer copper under the barrier.

Routing, decoupling, and stability numbers

Place a 100 nF X7R (0402/0603) between VDD–GND and VB–VS within 1–2 mm of the pins; add a 1–4.7 µF ceramic nearby for low‑frequency current. Put the series gate resistor at the device gate pad; 2–10 Ω is a practical starting range for Si/SiC, 1–3 Ω is common for eGaN, then tune by waveform. Use a Kelvin source/sense pad if the package offers it. Guard logic pins (IN/EN/FAULT/DESAT) with ground copper and avoid parallelism with HS/switch nodes. If switch‑node ringing persists, evaluate an RC snubber based on measured impedance; start from the ring frequency to extract C and choose R ≈ √(L/C).

Thermal pads, footprint, and MSL handling

For QFN/DFN, tie the exposed pad to the designated thermal/ground node with a via array (finished 0.2–0.3 mm drills on a 0.5–0.8 mm grid). Use a window‑pane stencil to target ~50–70% paste coverage on the exposed pad to limit float. Follow IPC‑7351 land patterns and the manufacturer’s recommended footprint and pin‑1 orientation. Check JEDEC J‑STD‑020 MSL; many SOIC are MSL 1, while QFN/DFN are often MSL 1–3 and may need baking if floor life was exceeded per J‑STD‑033.

GaN vs SiC driver pinouts—what actually differs?

GaN‑optimized drivers often run VDD around 5–6 V and duplicate OUT/COM pins in LGA/DFN to lower effective inductance; use all outputs/returns and stitch to the device source with multiple vias. Many SiC drivers expose VEE for −2 to −5 V turn‑off and a Miller clamp/CLAMP pin; route the clamp return to the same COM/HS node as the gate return. DESAT lines must be short, referenced to their quiet return, and filtered per the datasheet to avoid false trips at high dv/dt.

What should purchasing and layout include for a gate‑driver PCB build?

Provide the driver datasheet and exact package code (e.g., SOIC‑16 wide vs narrow, QFN body and pitch), the target FET/IGBT/GaN model and intended VGS/VEE, isolation working voltage and required creepage, the approved footprint source, exposed‑pad stencil coverage, and any pin‑swap/part‑sub rules. We can build and inspect to IPC Class 2 or Class 3 acceptance criteria, support RoHS and REACH compliance, and operate under an ISO 9001:2015 certified quality management system (SGS certificate CN‑2023‑Q1156, valid until June 2027). Quotes are returned within 24 hours and DFM feedback within 1 business day, so footprint and creepage checks happen before fabrication.