What caught teams off guard in PCB assembly? 10 pitfalls and fixes

The most common assembly surprises are insufficient paste transfer, missing or poor fiducials, via‑in‑pad solder wicking, panel designs that don’t match the pick‑and‑place flow, finish flatness issues under fine‑pitch parts, and BOM or MSL oversights.

Stencil and solder paste transfer

For 0402s and 0.5 mm‑pitch QFN/BGA, 100–130 µm (4–5 mil) laser‑cut, electropolished stencils are typical. Keep aperture area ratio ≥0.66 to avoid poor release; reduce pad apertures 5–10% for most chips to limit bridging. For QFN thermal pads, a windowpane pattern at 50–70% total paste coverage helps reduce voids (see IPC‑7093). Use T4 paste for 0.5 mm and T5 for 0.4 mm pitch. If the soak zone is too short or peak too low, expect graping and starved joints; too hot or too fast ramps drive balling.

Why did my 0402s tombstone?

Unequal wetting forces cause lift. Common drivers: asymmetric pad geometry, one pad tied to a large copper pour without balanced thermal relief, or uneven paste volumes. Match pad lengths within ~50 µm, keep equal copper thermal mass or use symmetric thermal spokes, and keep soldermask openings consistent. Reflow with a controlled soak (per J‑STD‑001/IPC‑A‑610 limits) to minimize wetting timing skew.

Via‑in‑pad and BGA voiding

Open or just‑tented vias in pads wick solder and starve the joint. For BGA/QFN pads, specify filled and capped vias per IPC‑4761 Type VII when using via‑in‑pad, especially at ≤0.5 mm pitch. BTC/QFN thermal pads benefit from paste windowing to keep voiding typically under ~25% area; verify with X‑ray and acceptability per IPC‑A‑610 Class 2/3.

Finish flatness vs fine pitch — ENIG or HASL?

Leaded HASL can show step height and coplanarity variation on small pads; fine‑pitch QFN/BGA (≤0.5 mm) and 0201/01005 parts typically prefer ENIG or ENEPIG for flatness and consistent wetting. Typical ENIG stack: Ni 3–6 µm, Au 0.05–0.1 µm. If you must use HASL, increase aperture reductions and expect tighter print control.

Fiducials, polarity, and readable text

Provide three global fiducials on the panel and at least two local fiducials near each fine‑pitch device. A common recipe: 1.0 mm bare‑copper dot with 2–3 mm soldermask clearance, free of silkscreen within 1 mm. Reference designators at 1.2–1.5 mm text height improve AOI readability. Keep silkscreen off pads; add unmistakable Pin‑1 and polarity marks aligned with the package standard (IPC‑7351).

Panelization and X‑outs — what did we miss?

Add 5–10 mm rails with tooling holes and global fiducials. For mouse‑bites, 0.4–0.5 mm perforation holes at 0.8–1.0 mm pitch with a 2–3 mm web deburr cleanly; keep components ≥2 mm from break edges. Define allowed X‑out rate per array and include barcode/array ID location. If your assembly requires selective wave or glue, confirm rotation and conveyor flow before you lock the panel.

BOM clarity, alternates, and MSL handling

BOM line items should include full MPN, approved alternates, and no‑mix rules for passives when matching is critical. Call out the moisture sensitivity level; MSL 3+ parts need dry packing and bake on seal breach per J‑STD‑033. Include labeling instructions for lot/date code recording and place any required UID on the rail.

Test access and in‑system programming

For ICT, route 0.75–1.0 mm bare copper test pads on a 2.54 mm grid with soldermask clearance and keepouts for probe tips. If you only need flying‑probe or pogo access, 0.5–0.9 mm pads on dedicated nets work. Reserve SWD/JTAG/UART pads or a Tag‑Connect footprint; avoid programming through high‑ESD connectors without protection.

Reflow profile and component limits

Confirm component MSL and Tmax (J‑STD‑020). For SAC305, many profiles target 235–250 °C peak with 30–90 s above liquidus and ΔT across the board under ~10–15 °C. Heavy copper pours under small parts can create local cold spots; balance copper or use paste‑mask adjustments and profile per the heaviest region.

Quick checks before release

• Stencil thickness, aperture reductions, and QFN windowing meet area‑ratio ≥0.66

• Local/global fiducials placed with clear mask clearance and no silkscreen

• Finish matches pitch: ENIG/ENEPIG for ≤0.5 mm and 0201s

• Any via‑in‑pad is IPC‑4761 Type VII filled and plated

• Panel rails, break‑away design, barcodes, and X‑out rules defined

• ICT or pogo test pads present; ISP header/footprint reserved

• BOM has alternates; MSL/bake notes included; polarity and Pin‑1 marked

• Acceptance class called out (IPC‑A‑610 Class 2 or 3)

Manufacturing criteria and compliance

Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria. RoHS and REACH compliance is supported for hazardous substance control. Our quality management system is ISO 9001:2015 certified (certificate CN‑2023‑Q1156 by SGS, valid to June 2027), aligning build and inspection with documented procedures.

DFM collaboration, before you spin again

Share your Gerbers, centroid, stencil spec, panel drawing, and reflow limits; you’ll get practical DFM notes that target paste transfer, fiducials, via‑in‑pad treatment, panel flow, and test access before you commit a new stencil.