What Caught You Off Guard During PCB Assembly? Concrete fixes that work

Most teams are caught off guard by data mismatches (XY/rotation), stencil-paste choices, and BOM ambiguities that halt pick-and-place or cause solder defects in the first build.

Are your XY and rotations machine-ready?

• Supply one centroid per assembly side with: RefDes, X, Y, Rotation, Side, MPN. State units (mm or mil) and rotation convention (0° with pin‑1 at upper‑left, CCW positive). Mixing CW/CCW or mm/mil silently misplaces parts.

• Verify origin: board datum at lower‑left of the routed outline (not panel, not paste layer). Include a clear board outline Gerber/mech layer.

• For polarized parts, confirm that 0° in XY matches silkscreen/paste/library orientation. A single 90° mismatch can flip every diode in a row.

Stencil thickness and apertures for fine pitch

• Typical starting points: 100–120 µm (4–5 mil) stainless stencil for 0402–0603 and 0.5 mm QFN. Step‑down to 75 µm (3 mil) under 0.4 mm BGA/QFN. Keep area ratio ≥ 0.66 for reliable release.

• Reduce apertures 5–10% on small passive pads to curb tombstoning; add home‑plate or inverted‑home apertures for 1206/0805 if skew shows up in first articles.

• For thermal pads on QFN/DFN, windowpane the paste to 50–70% coverage; add 0.2–0.3 mm solder dams to limit float.

Fiducials, panel rails, and tooling holes

• Global fiducials: three per panel, 1.0 mm bare copper with 2.0 mm soldermask clearance, opposing corners asymmetrical to prevent mirroring.

• Local fiducials: two per fine‑pitch device (≤0.5 mm pitch), placed within ~10–15 mm.

• Panel rails: 5–10 mm on at least two opposite sides. Tooling holes: 3.0 mm non‑plated, 5 mm from board edge, keep copper ≥1.5 mm away.

• V‑score keepout: ≥0.3 mm from score to copper; tab‑route mouse‑bites: 0.3 mm holes, ~0.5 mm pitch, tab width 2–3 mm.

Where BOMs derail PnP and purchasing

• One line, one MPN. If alternates are allowed, list approved MPNs there—don’t put them in notes.

• Call DNP explicitly in the BOM (Qty=0 or DNP column), not only on the schematic.

• State tolerances and dielectric (e.g., X7R vs X5R) for passives; voltage rating for caps; contact plating for connectors.

• Lifecycle flags (NRND/EOL) and package codes (e.g., SOT‑223 vs DPAK) prevent last‑minute scrambles.

• Overage guidance: 0402/0603: +3–5%; connectors: +1 pc; BGAs/QFNs: +1–2 pcs; unique/coiled parts: consult CM when reels aren’t possible.

Moisture sensitivity and handling surprises

• MSL matters: common MSL3 parts have 168 h floor life at ≤30°C/60% RH once unsealed; baking (e.g., 125°C for 24 h) may be required after exposure.

• Prefer reels; for cut tape, provide ≥200–300 mm leader/trailer. BGAs/QFNs: supply full JEDEC trays when possible.

• Label polarity/orientation on reels and trays; mixed orientations in cut tape are frequent escapees.

Polarity, pin 1, and markings that survive production

• Put pin‑1 on silkscreen and copper (dot/chamfer/corner). For diodes, mark the cathode with a bar on both mask and silk near the body.

• Don’t rely solely on mask openings—solder can obscure them. Keep marks ≥0.15 mm stroke and ≥0.2 mm mask clearance.

Via‑in‑pad, mask dams, and unintended wicking

• If you use via‑in‑pad under BGAs/QFNs, specify filled and capped vias; open vias wick paste and starve joints.

• Maintain 0.1–0.15 mm soldermask dam between fine‑pitch pads; if not feasible, tune apertures to control bridging.

Reflow profile expectations you should state

• Lead‑free SAC305 baseline: ramp 1–3°C/s; time above liquidus (217°C) 60–90 s; peak 240–245°C; cool 3–4°C/s. Heavy copper or dense ground planes may need profile tweaks.

• If double‑sided, declare which side first and any tall‑part keepouts to avoid secondary‑side drop.

Cleaning, no‑clean, and coating compatibility

• If you need no‑clean residue for RF stability, say "Do Not Wash". If you will conformally coat, specify cleaning requirement and keepouts; many no‑clean fluxes cause coating adhesion issues unless cleaned.

ICT/functional test pads that actually work

• Target 0.9–1.0 mm (36–40 mil) pad diameter, ≥1.27 mm pitch for spring probes; mask‑defined pads with no solder paste. Keep ≥2.0 mm keepout around tall components for probe heads.

Pre‑assembly checklist you can copy

• Gerbers/ODB++, paste layers, board outline, centroid per side with units/origin/rotation convention

• BOM with one MPN per line, alternates listed, DNPs explicit, tolerances/ratings set

• Panel drawing with rails/fiducials/tooling holes, depanelization notes

• Stencil thickness and any step areas; special apertures (thermal, home‑plate)

• Handling notes: MSL, cleaning/coating, double‑sided order, overage plan, packing

Quality, compliance, and how we inspect

• We can build and inspect to IPC Class 2 or IPC Class 3 acceptance criteria. RoHS and REACH compliance is supported for material control. Our quality management system is ISO 9001:2015 certified (SGS, CN‑2023‑Q1156, valid to Jun‑2027).

Fast feedback prevents most of these surprises

• Early DFM catches panel, stencil, and data issues before kitting. We return quotes within 24 hours and DFM feedback within 1 business day, so you can correct risks before the first paste print.