Ground plane split vs continuous on high‑current PWM + ADC boards

Split vs continuous: the short answer

Use a continuous ground plane. Do not split the reference plane under any signal; instead, confine high di/dt power returns and the switch‑node’s parasitic capacitance with placement, local copper, keepouts, and stitching vias.

Where does the return current really flow?

At low frequency, return current spreads through the plane by resistance (sheet ~0.49 mΩ/sq for 1 oz Cu). At high frequency, it follows the path of least inductance directly under the outgoing trace. If you cut a slot in the plane, the return detours around the gap, loop area grows, and both EMI and ground bounce increase. For a 20 A motor phase step in 20 ns (dI/dt ≈ 1 A/ns), 10 nH of loop inductance creates about 10 V of disturbance (V = L·dI/dt)—this is what ruins your ADC more than milliohms of DC drop.

PWM power stage layout and plane strategy

• Keep the hot loop (FETs/diode or synchronous FET, switch node, and the ceramic input caps) as small as possible; target ≤5 mm trace lengths and tightly coupled return to the solid GND on the adjacent layer.

• Place a solid GND plane directly under the power stage layer. Do not split it; instead, add a local keepout only under the switch node copper to reduce displacement current into the plane.

• Stitch the ground plane around the power stage with vias at 1–2 mm pitch to confine fields and provide multiple low‑L return paths.

• Put the bulk cap loop (VIN+, bulk cap, VIN−) compact and adjacent to the FETs; place several 0.1–1 µF X7R MLCCs directly across VIN and GND pins of the power stage.

• Use dedicated, wide returns for gate‑driver and bootstrap grounds that go straight down into the GND plane via their own vias next to the pins.

• Keep any trace crossing a plane gap at zero; if a gap is unavoidable for safety, bridge it with high‑frequency capacitors arranged to give the signal a return path at the frequencies it carries.

ADC ground, reference, and input filtering

Define a quiet ground node for the ADC by placement, not by splitting planes. Bring the ADC ground pin and VREF return to the plane through their own vias into a low‑current area, away from the power stage return vias by several millimeters of copper distance. Tie sensor returns to this node with Kelvin traces. For a 12‑bit ADC at 3.3 V, 1 LSB ≈ 0.8 mV; keep ground error at the ADC pins below ~0.5 mV under load. A practical RC at each ADC input is 100–470 Ω in series and 1–10 nF to the local quiet ground near the pin. Example: 100 Ω + 4.7 nF gives fc ≈ 338 kHz and τ = 0.47 µs; five time constants is 2.35 µs, often acceptable for MCU ADC acquisition windows. Ensure the ADC’s effective source impedance meets its datasheet (commonly <1 kΩ).

Do split planes ever help?

Rarely, and not for separating “AGND” and “DGND” on the same low‑voltage board. Splits are valid for safety creepage/clearance or to deliberately remove plane under the switching node to cut its capacitance. If you must define separate copper regions (e.g., sensor shield vs power return), connect them at a net‑tie near the point where the measurement is defined, and verify no high‑edge‑rate trace crosses the gap. Avoid ferrite‑bead “AGND–DGND” links for large return currents; they saturate and create unpredictable impedance versus frequency and DC bias.

How do I verify ground noise and ADC error?

Probe differentially between the ADC ground pin and the power stage ground near the FET source or current shunt during worst‑case PWM edges. With a spring‑tip ground, you should see <0.5 mV pk‑pk for a clean 12‑bit system at 3.3 V. Also measure the switch‑node dV/dt and confirm your keepout reduces plane‑to‑node capacitance (lower common‑mode current at each edge). Correlate ADC noise with PWM phase events; if correlation remains, shorten the hot loop and move the ADC ground vias farther from power returns.

Stackup and impedance hints for 4 layers

A proven stack is L1: components + power stage routing, L2: solid GND, L3: power distribution + slow signals, L4: signals (with local GND pours stitched frequently). Keep L1–L2 spacing small (≈0.1 mm core) to cut loop inductance; use 1–2 oz copper where current density demands. Guard sensitive analog traces with grounded copper on the same layer and stitch to the plane every 2–3 mm. Keep at least 3–5 mm clearance between the switch node copper and any sensor/ADC routing, with a via‑stitched ground fence in between.

Control edge rate, not just frequency

PWM at 20–100 kHz is common, but EMI and ground bounce scale with edge rate. Use gate resistors, snubbers, and appropriate device selection to tame dV/dt and dI/dt. Reducing dV/dt by half often helps more than moving PWM frequency by a decade.

Current sensing and Kelvin paths

If using a shunt, route true Kelvin pairs from the shunt to the amplifier/ADC. Return the sense amplifier ground directly to the shunt’s cold end, not to a generic ground pour. Keep the amplifier and its RC filter close; give its supply decoupler a dedicated return via into the quiet plane area.

Manufacturing and acceptance notes

We can build and inspect to IPC Class 2 or IPC Class 3 acceptance criteria. RoHS and REACH compliance is supported. Our quality management system is ISO 9001:2015 certified (certificate no. CN-2023-Q1156, SGS, valid until June 2027). If you want a quick design sanity check before fab, we return quotes within 24 hours and DFM feedback within 1 business day.