HDI PCB Design Guide PDF: Stackups, Vias, Rules, Checklist

This is a practical HDI PCB design guide you can print to PDF.

What is HDI and when is it worth it?

HDI (High Density Interconnect) uses microvias, thin dielectrics, and fine lines to route high‑pin‑count BGAs, shrink layer count, or control impedance in tight envelopes. Typical triggers: 0.65–0.3 mm pitch BGAs, >10 Gbps links, or weight/height limits where 1+N+1 or 2+N+2 beats through‑hole fanout.

Field‑proven HDI stackups

Common builds per IPC‑2226 nomenclature:

• 1+N+1: laser microvias L1↔L2 and Ln↔Ln‑1, with a plated through core. Good for 0.5–0.65 mm BGA escape and short high‑speed paths.

• 2+N+2: two sequential lam cycles with stacked or staggered microvias. Used for 0.3–0.5 mm BGA, dense RF/mixed‑signal.

Typical materials: FR‑4 high‑Tg (Tg 170–180 °C), εr ~3.5–3.8. Use thin, spread‑glass prepregs (1067/1080) for HDI dielectric layers (50–100 µm per lam cycle). Avoid coarse 7628 adjacent to high‑speed layers to reduce skew.

Which microvias and how many stacks?

• Laser microvias: finished hole Ø 75–125 µm, capture pad 225–300 µm. Keep annular ring ≥50–75 µm.

• Depth rule: laser microvia aspect ratio ≤1:1 (dielectric thickness roughly equals drill diameter). 60–100 µm dielectric per blind step is practical.

• Stacking: stagger where possible for best reliability. If stacking, limit to 2‑high stacks and copper‑fill lower vias before stacking the next via per IPC‑2226 guidance.

• Skip vias (L1→L3) are possible with controlled dielectric; verify with your fabricator’s lam data.

• Through‑hole vias: aspect ratio ≤8:1 to 10:1 is broadly manufacturable; keep finished Ø ≥0.2–0.3 mm on dense HDI cores.

Via‑in‑pad and filling for BGA escape

For 0.4–0.5 mm pitch BGAs, VIPPO (via‑in‑pad, plated over) is often required. Use copper‑filled microvias on pad, then planarize and cap plate to keep assembly void‑free. Resin‑filled blind vias are acceptable for non‑stacked cases; use copper‑filled when stacking or carrying high current. Keep solder mask openings cleanly registered; avoid mask slivers <75 µm.

Practical minimums for lines, spaces, pads

• Outer layers: 60–100 µm line/space is widely available; advanced HDI can go to 50 µm. Start designs at 75 µm unless analysis proves margin.

• Inner layers: 75–125 µm line/space improves yield and etch control.

• BGA fanout: for 0.4 mm pitch, pad 0.23–0.25 mm NSMD with 0.1 mm microvias in‑pad is common; route 60–75 µm lines between pads only if mask and etch allow.

• Anti‑pads/clearances: keep ≥200–250 µm around through‑holes in plane layers to control impedance discontinuities and reduce CAF risk.

Hitting 50 Ω and 90–100 Ω impedance

Use a field solver for final values; IPC‑2141 equations are fine for first pass. Typical starting points on FR‑4 (εr ~3.6–3.8), 18 µm copper:

• Microstrip 50 Ω over 100 µm dielectric: w ≈ 0.18–0.22 mm.

• Microstrip 50 Ω over 60 µm dielectric: w ≈ 0.12–0.16 mm.

• Differential 100 Ω over 100 µm dielectric: w ≈ 0.15–0.20 mm, s (edge‑to‑edge) ≈ 0.15–0.22 mm.

• Coated stripline 100 Ω (two‑plane) with 100 µm dielectrics: w ≈ 0.10–0.14 mm, s ≈ 0.12–0.18 mm.

Keep reference plane continuity. Add stitching vias near layer transitions; ≤1–2 mm pitch along high‑speed edges is a practical start. Request impedance coupons and acceptance per IPC‑6012.

Power, planes, and copper balance

Thin dielectrics raise plane capacitance; leverage this for PDN targets. Maintain copper balance across the panel and per lamination to minimize warp; add thieving where areas fall below ~30% copper. Avoid large plane voids under stacked microvia clusters; use local keepouts instead of massive anti‑pads.

Reliability notes for stacked microvias

Most early failures localize at the filled‑via to cap interface. Reduce risk by: limiting stacks, using copper‑filled vias, keeping current density reasonable (derate stacked‑via current vs. equivalent through‑hole), and aligning capture pads precisely. Keep thermal excursions (reflow cycles) in mind during reliability modeling.

Test, acceptance, and compliance

Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria. RoHS and REACH compliance is supported for hazardous substances. Define microsections that cut through stacked and staggered regions, and specify HDI coupons for impedance and plating thickness verification. [Ref: IPC‑6012, IPC‑2226]

Printable HDI PCB checklist (save as PDF)

• Choose stackup: 1+N+1 or 2+N+2; set dielectric per blind step to 60–100 µm with spread‑glass

• Select microvia scheme: staggered preferred; limit stacks to 2‑high; define copper‑fill where stacking

• Set rules: outer 60–100 µm, inner 75–125 µm; mask dam ≥75 µm; annular rings ≥50–75 µm (microvia), ≥100–150 µm (through‑hole)

• Impedance: target 50 Ω single‑ended, 90–100 Ω differential; request coupons and solver report

• VIPPO where needed; specify copper‑fill and cap plating; define via tenting/mask

• PDN: plane splits, decoupling escape, copper balance/thieving plan

• Reliability: reflow profile, via current, thermal cycling assumptions

• DFM package: Gerber/ODB++, stackup table, drill map, material set, impedance table, class (2/3)

How to get a fast DFM and quote?

Include Gerbers/ODB++, stackup, materials, impedance table, and BGA pitch info. You’ll receive a quote within 24 hours and DFM feedback within 1 business day.

Certifications relevant to procurement

HyperPCB operates an ISO 9001:2015 certified quality management system (certificate CN‑2023‑Q1156 by SGS, valid through June 2027). Our partner factory AEGIS maintains ISO 9001:2015, ISO 14001:2015, and ISO 45001:2018, plus ISO 13485:2016 and IATF 16949. These frameworks align with IPC Class 2/3 builds and substance controls noted above.