How do I eliminate noise on my custom PCB?

Eliminate noise on a custom PCB by shrinking current loops, keeping a solid ground reference, controlling impedance and edge rates, decoupling each IC pin, filtering I/O, and verifying with near-field probes and pre-compliance tests.

Is your ground plane continuous?

A continuous ground plane is the single biggest EMI win. Never route high-speed or clock nets over splits, slots, or gaps—return current will detour and radiate. Stitch any necessary plane transitions with a ground via next to every signal via. Around board edges and between noisy and quiet areas, add via fences at 5–10 mm pitch; tighten to 2–3 mm if you need shielding effectiveness up to a few hundred MHz. Keep openings and slots under 1/20 of the wavelength of your highest significant harmonic (for a 1 ns edge, ~350 MHz, wavelength in FR-4 ≈ 428 mm, so keep slots <21 mm). Minimize loop area: route supply pins to their decouplers and to the ground plane with the shortest, widest geometry you can manage.

Power distribution and decoupling values

Design the PDN with a target impedance: Ztarget = Vripple / Istep. Example: a 1.2 V core rail with 1% ripple (12 mV) and a 0.8 A load step gives Ztarget ≈ 15 milliohm. Use parallel MLCCs to keep PDN impedance below that out to tens of MHz. Place a 0.1 uF (X7R, 0402/0603) at every VDD pin within 1–2 mm of the pad, route with two short vias (power and ground) to minimize ESL, and add local bulk 4.7–22 uF per rail (low-ESR ceramic or polymer). For BGAs, via-in-pad helps—if not possible, keep the loop area from pin to cap to plane under ~10 mm^2. Use wide pours for power, avoid daisy-chaining long thin traces that raise inductance. If rails are noisy, add an LC or ferrite bead (e.g., 600 ohm at 100 MHz) to isolate analog sections; check bead DC bias curves so the impedance remains high at your operating current.

Are your signals controlled and terminated?

Control impedance and you control reflections. Typical targets: 50 ohm single-ended microstrip, 90 ohm differential for USB 2.0 HS, 100 ohm differential for Ethernet and many LVDS links. Use an IPC-2141-based calculator or a field solver against your exact stackup. Terminate fast edges: a 10–33 ohm series resistor at the source often damps ringing on short clock lines. Keep stubs short—rule of thumb is under 1/10 of the electrical length corresponding to your edge speed: l ≈ (tr * v) / 2. With tr = 1 ns and FR-4 velocity ~150 mm/ns, keep stubs <7.5 mm. Reduce crosstalk with the 3W rule: spacing between parallel runs ≥ 3x trace width, and route orthogonal directions on adjacent layers. For differential pairs, keep spacing constant, avoid plane splits, and match lengths tightly enough to keep intra-pair skew a small fraction of the unit interval.

Filter I/O and isolate domains

Cables are antennas. Add common-mode chokes on external ports (USB, Ethernet, LVDS camera) and place them right behind the connector. Put ESD/TVS diodes within 2–3 mm of the connector pins, with the shortest return to chassis or ground. Partition noisy and sensitive blocks: switchers, digital cores, and high dV/dt nodes stay together; precision ADCs, references, and high-gain analog stay away. If you must split grounds for functional reasons, connect them at a single point under the ADC or at the entry of an analog island and keep high-speed signals entirely on one side of the split. For very sensitive analog, guard traces tied to ground and via-stitched every 2–5 mm can reduce coupling. Shield cans help if the layout work isn’t enough; keep ventilation holes smaller than 1/20 wavelength of the problem frequencies.

How do you verify noise reduction?

Before certification, do fast checks: use H-field and E-field near-field probes with a spectrum analyzer to sniff hot spots (clocks, DC/DC edges, long I/O). For conducted emissions, test at 150 kHz–30 MHz with a LISN if you can. Correlate peaks with time-domain edges; often a small series resistor or a gate-rate change in firmware drops a harmonic cluster. Clamp-on ferrites on problem cables can confirm common-mode issues; replace the clamp with a designed-in common-mode choke when proven. Add test pads for key rails and clocks so you can probe without long ground leads; use spring ground probes to avoid measurement-induced loops.

Example stackups and spacing

Common 4-layer starting point: L1 signals, L2 ground, L3 power, L4 signals. With FR-4 (effective Er ~4.2) and a 7628 pre-preg (dielectric ~0.18 mm) over 1 oz copper, a 50 ohm microstrip on L1 is typically around 0.30–0.35 mm wide; verify with a solver. A 100 ohm differential pair can often be achieved near 0.20 mm width with 0.20 mm gap on the same dielectric. Keep high-speed traces at least 3x their width from board edges and plane voids; keep pairs ≥3x dielectric height from any split or cutout.

Pre-fab noise-reduction checklist

• Continuous ground plane; no high-speed over splits; stitching vias near signal vias

• 0.1 uF at every VDD pin within 1–2 mm; bulk 4.7–22 uF per rail; bead/LC where needed

• Controlled impedances (50/90/100 ohm) confirmed against the real stackup

• Series terminations (10–33 ohm) on fast single-ended clocks; minimal stubs

• 3W spacing, orthogonal adjacent layers; guarded sensitive nets where required

• Common-mode chokes and ESD diodes at connectors; shortest returns to ground/chassis

• Via fences 5–10 mm around edges/noisy zones; shield cans if layout fixes fall short

• Pre-compliance scan with near-field probes; correlate peaks and iterate quickly

Procurement notes

Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria. HyperPCB operates an ISO 9001:2015 certified quality management system (SGS certificate CN-2023-Q1156, valid to June 2027) and supports RoHS and REACH compliance for hazardous substance control.