How do I get an accurate PCB manufacturing quote fast?

Submit a complete, unambiguous data pack—Gerbers/ODB++, fab notes, stackup, drills, finishes, impedance, and tests—so pricing needs no assumptions.

What information do fabricators need for a quote?

• Fabrication data: ODB++ or full Gerber set (RS-274X), NC drill/drill map, IPC-356 netlist if available

• Fab drawing: outline, layer count, overall thickness (e.g., 1.6 mm), copper weights per layer (e.g., 35 µm/1 oz outer, 17–35 µm inner), soldermask/silkscreen colors, peelable mask areas if any

• Material: laminate/prepreg family and Tg; for RF/low-loss provide vendor/grade and Dk/Df at frequency (e.g., FR-4, Dk≈4.2 @1 GHz; or low-loss Dk≈3.0–3.5)

• Design rules: minimum trace/space (e.g., 0.10 mm/4 mil), minimum finished drill (e.g., 0.20 mm), target aspect ratio (board thickness / min drill), minimum annular ring (e.g., 0.10–0.15 mm)

• Vias: through, blind/buried, microvia (laser), via-in-pad (VIPPO), backdrill requirements, fill type (resin/conductive)

• Impedance: targets and tolerance (e.g., 50 Ω SE, 90 Ω diff, ±10%), layer assignments, preferred stackup hints (core thicknesses or dielectric thicknesses)

• Surface finish: ENIG, HASL lead-free, ENEPIG, OSP; note gold thickness if controlled

• Testing/acceptance: 100% E-test (IPC-9252), IPC Class 2 or Class 3, microsection/X-ray if needed

• Compliance: RoHS/REACH, halogen-free if required

• Quantities and delivery batches: prototype vs. production volumes, panelization or array drawing if you have it

Cost drivers you can control

Layer count and lamination cycles dominate cost; blind/buried microvias add extra lam cycles and laser drill steps. Minimum features set yield: 4/4 mil trace/space and 0.20 mm finished drills typically cost less than 3/3 mil and 0.15 mm. Copper weight increases plating/etch time; 2–3 oz outer layers cost more than 1 oz. Aspect ratio beyond ~8–10:1 for mechanical through-holes (e.g., 1.6 mm board with 0.20 mm drills is 8:1) drives risk and scrap. Tight impedance (±5–8%) may require narrower dielectric tolerance and coupon measurement; ±10% is more economical. ENIG generally prices above lead-free HASL; ENEPIG prices above ENIG. Backdrilling, controlled depth routing, and via-in-pad with resin fill add process time and yield risk, impacting quote.

Impedance control and stackup notes

If you need 50 Ω microstrip on L1 with 35 µm copper over FR-4 (Dk≈4.1–4.3), a dielectric thickness in the ~0.18–0.23 mm range is typical for 4–5 mil traces per IPC-2141 first-order estimates; verify with your fabricator’s field solver. For 90 Ω differential stripline pairs on inner layers, specify pair spacing, copper weight, and target dielectric thicknesses between planes. Call out which nets need impedance, the tolerance (±10% common), and whether test coupons are required per IPC-6012. Provide acceptable alternative stackups (e.g., swap a 2116 for a 7628 prepreg) to preserve impedance while improving availability.

Via choices, drills, and aspect ratio

Through-holes keep costs down. Blind/buried vias are justified for dense BGAs or when escape routing cannot meet 4/4 mil rules. Laser microvias (≤0.10–0.125 mm) should end on copper pads and are typically limited to 1-n-1 structures for yield; stacked microvias cost more than staggered. Maintain annular ring ≥4 mil (0.10 mm) on PTH pads when possible. If you require backdrilling to remove stubs, specify remaining stub length (e.g., <0.25 mm) and which nets/layers are affected.

How to speed up quoting and DFM feedback?

Supply ODB++ or IPC-2581 to avoid layer-mapping ambiguity. Include a readme outlining material intent, impedance targets, and any must-haves vs. nice-to-haves. Name files clearly (L1_TOP.gbr, L2.gbr, Drill_PTH.xln, etc.). Run a final DRC and netlist compare; include IPC-356 for CAM validation. Provide panel or array drawing if you need specific fiducials, tooling holes, or breakaway tabs; otherwise allow the fabricator to optimize panel utilization. If time-to-quote matters, give latitude: “ENIG or ENEPIG acceptable,” or “90 Ω diff ±10%.” HyperPCB returns quotes within 24 hours and DFM feedback within 1 business day, so complete data directly shortens cycle time.

Compliance and acceptance criteria

HyperPCB operates an ISO 9001:2015 certified quality management system (certificate CN-2023-Q1156, SGS, valid to June 2027). Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria, and RoHS/REACH compliance is supported for substance control. Our partner factory AEGIS maintains ISO 9001:2015, ISO 14001:2015, and ISO 45001:2018 systems, plus ISO 13485:2016 for medical and IATF 16949 for automotive. AEGIS also manufactures high‑frequency laminates and supplies RF PCB fabricators in China, which helps when low‑loss materials or RF stackups are required.

What if I don’t know the exact stackup?

Share targets instead: overall thickness (e.g., 1.6 mm), copper weights, impedance values and tolerances, and preferred laminate family. A CAM engineer can propose a stackup with available cores/prepregs that meets 50 Ω/90 Ω goals and matches your mechanical constraints.

Quick pre-checks before you request a quote

Confirm layer polarity, eliminate soldermask openings over vias unless tenting needed, ensure silkscreen doesn’t overlap exposed copper, and check copper-to-edge clearance (e.g., ≥0.25 mm). Add controlled depth notes for countersinks/counterbores. These small fixes prevent DFM holds and re-quotes.