How much does a 4‑layer PCB cost? What actually sets the price

A 4‑layer PCB has no single price; it is set by used panel area, order quantity, and feature complexity.

What does a 4‑layer PCB cost? The short answer

Without your outline, stackup, finish, vias, tolerances, and quantity, any number is guesswork. Per‑board price is dominated by how efficiently your design fits on a production panel, plus adders for features such as ENIG, higher copper, fine lines/drills, controlled impedance, and acceptance class.

Primary cost drivers for 4‑layer fabrication

• Panel utilization and board outline: price scales with the area you consume on a standard production panel (commonly 18×24 in / 457×610 mm). Odd outlines, large keep‑outs, and wide break‑tabs waste area.

• Surface finish: LF HASL is the simplest; ENIG improves flatness and shelf life; hard gold is for edge connectors.

• Copper weight: 0.5–1 oz (18–35 µm) outer copper is mainstream; 2 oz (70 µm) raises etch compensation needs and process time.

• Minimum trace/space and registration: ≤3/3 mil features and tight copper‑to‑board edge clearances increase imaging and alignment difficulty.

• Drills and vias: finished drills <0.25–0.30 mm, high drill count, via‑in‑pad with fill/cap, or blind/buried/microvias add steps.

• Controlled impedance: requires coupons, measurement, and documentation per IPC‑6012/IPC‑2221/IPC‑2141 targets.

• Laminate system: standard FR‑4 (Tg ≈135–150 °C) is most economical; high‑Tg FR‑4 (≈170–180 °C), halogen‑free, or RF/PTFE hybrids cost more.

• Acceptance and test: 100% electrical test, tighter ICT/fixture pads, and IPC Class 3 inspection raise touch‑time.

• Solder mask and legend: non‑green masks, two‑color legends, or high‑opacity inks increase processing passes.

How does panel utilization change per‑board price?

Fabricators build on fixed‑size panels; you pay for the panel area your array consumes. As a sizing example (geometry only): on an 18×24 in panel, a 100×100 mm board often arrays at 4×5 (20 pcs) with rails and tooling; a 50×50 mm board can array at high counts but may need extra rails to maintain rigidity. Add realistic rail widths (for example 8–12 mm) and part‑to‑part spacing (for example 2–3 mm) before you compute fit. Small adjustments to outline, tab style, or rotating parts 90° can change the piece count by an entire row or column, which materially shifts per‑board cost.

Which 4‑layer stackups are common?

A mainstream 1.6 mm build uses FR‑4 with outer copper 1 oz (35 µm) and cores/prepregs such as 0.5–0.8 mm cores paired with 2116/7628 or 1080/2116 prepregs. For tighter impedance or fiber‑weave skew control, many designers choose dual‑1080 or 2116/1080 combinations. Typical impedance targets: 50 Ω single‑ended and 90 Ω differential are common on outer or inner signal layers; confirm final values with your fabricator’s dielectric data and etch factors.

Do controlled impedance or IPC Class 3 increase cost?

Yes, both typically add process and inspection steps. Impedance control needs coupons and measurement records; Class 3 raises requirements for annular rings, cleanliness, and defect acceptance per IPC‑6012. HyperPCB builds and inspects to IPC Class 2 or Class 3 acceptance criteria.

Practical ways to control cost without risking yield

Use a standard 4‑layer FR‑4 stackup when performance allows. Keep outer layers at ≥4/4 mil and finished drills ≥0.30 mm where density permits; consolidate drill sizes to reduce tool changes. Avoid blind/buried vias and via‑in‑pad unless density, routing, or RF current return justify them. Choose LF HASL when ENIG’s coplanarity or Ni/Au interface is not required by components. Panelize thoughtfully: align array dimensions to common panel sizes, add stable rails, and pick break‑tab styles that balance rigidity and depanel ease. Minimize the number of impedance variants and accept standard tolerances (often ±10%) if the design allows.

What to include in an RFQ for a fast quote?

Provide Gerber or ODB++; fabrication drawing with outline and finished thickness (for example 1.6 mm); copper weights per layer (for example 1 oz outer/inner); surface finish (LF HASL, ENIG, etc.); solder mask and legend colors; minimum trace/space and finished drill sizes; via types (through, blind/buried, via‑in‑pad) and any fill/cap requirements; controlled‑impedance nets and targets (for example 50 Ω, 90 Ω) with tolerance; acceptance criteria (IPC Class 2 or Class 3); RoHS/REACH requirement; quantity and preferred panelization; electrical test and special inspection notes.

Verification and turnaround

HyperPCB operates an ISO 9001:2015 certified QMS (SGS certificate CN‑2023‑Q1156, valid until June 2027). Quotes are returned within 24 hours and DFM feedback within 1 business day. Boards can be built and inspected to IPC Class 2 or IPC Class 3, and RoHS/REACH compliance is supported.

Notes

This article explains cost drivers and geometry; it does not publish price tables. Send your design data for a firm quotation based on your actual stackup, features, and quantity.