How to choose a PCB manufacturing company: standards, stackups, DFM checks

A dependable PCB manufacturing company proves capability with standards, measurable geometries, and documented processes. HyperPCB operates an ISO 9001:2015 certified QMS (certificate CN-2023-Q1156, SGS, valid to June 2027) and supports RoHS/REACH. We build and inspect to IPC Class 2 or Class 3, and return quotes within 24 hours with DFM feedback in 1 business day.

Which certifications and acceptance criteria matter?

• Fabrication acceptance should reference IPC-6012 for rigid boards and visual evaluation against IPC-A-600. Class 2 suits most commercial electronics; Class 3 targets high reliability where continuous service and safety margins are critical. HyperPCB supports Class 2/3 inspection and RoHS/REACH documentation. Our partner factory AEGIS maintains ISO 9001:2015, ISO 14001:2015, and ISO 45001:2018, plus ISO 13485:2016 for medical and IATF 16949 for automotive—useful when your end product must align with those regimes.

Impedance and stackup: numbers to specify

Impedance is controlled by dielectric height, copper thickness, dielectric constant (Dk), and trace geometry. Reference IPC-2141 (or a field solver) and request TDR coupons.

• Typical FR-4 Dk at 1 GHz: 3.6–4.2; common prepregs include 7628 with ~0.18–0.20 mm dielectric thickness per sheet.

• Outer layer 50 Ω microstrip on 35 µm (1 oz) copper with 0.18–0.20 mm dielectric to plane usually needs ~0.30–0.40 mm trace width (mask relief reduces effective Dk slightly).

• Inner layer 100 Ω differential stripline on 18 µm copper with ~0.10 mm dielectric to each plane often lands around 0.10–0.14 mm trace with 0.10–0.15 mm spacing (pair geometry and resin content shift this).

• Diff pairs at 90 Ω are common for USB/PCIe; ±10% impedance tolerance is a realistic fabrication target when you lock the stackup and resin content.

• Specify copper weights (typical: 18 µm inner, 35 µm outer) and roughness needs when loss matters; smoother foils reduce high‑speed loss.

What geometric limits should you design to?

Design to manufacturable minima unless HDI is justified by package pitch.

• Line/space: 100/100 µm (4/4 mil) is mainstream; 75/75 µm (3/3 mil) is achievable with tighter process windows and more stringent DFM.

• Through holes: finished 0.20–0.30 mm are common; keep aspect ratio ≤8–10 (board thickness to drill diameter).

• Laser microvias: 75–100 µm diameter, single‑level (L1–L2) preferred for yield; stacked/stacked‑and‑filled increase risk/cost.

• Annular ring: ≥0.10 mm (4 mil) target for plated through holes; capture pad ≈ hole + 0.20 mm is a practical starting point.

• Soldermask: dam ≥0.10 mm; relief 0.05–0.075 mm per side to avoid mask encroachment on pads.

• Copper‑to‑edge: ≥0.25 mm; drill‑to‑copper: ≥0.20 mm on mechanical drills helps with registration.

• Finishes: ENIG for flatness (BGAs), lead‑free HASL for robustness/cost, OSP when very thin copper is desired on fine‑pitch pads.

Materials for RF and high-speed work

For RF or SerDes above a few GHz, FR‑4 loss/variation often dominates. Hydrocarbon/ceramic or PTFE‑based laminates (Dk ≈ 2.2–3.5, tanδ ≈ 0.0009–0.003) keep loss and phase error in check. Our partner factory AEGIS manufactures its own high‑frequency laminates and supplies RF PCB fabricators in China, including publicly listed PCB companies—useful when you need controlled Dk lots, matched cores, and consistent foil profiles across builds.

DFM checklist you can paste into your fab notes

• Call out IPC-6012 class and IPC-A-600 visual class; request impedance coupons and TDR report

• Provide full stackup: copper weights per layer, dielectric thicknesses, resin content, target Dk/Df and vendor family

• Impedance targets and tolerance (e.g., 50 Ω SE, 90/100 Ω diff, ±10%) with trace layer assignment

• Min line/space, min drill (finished), min annular ring, soldermask dam, copper‑to‑edge; specify via aspect ratio limit

• Surface finish, soldermask color/gloss, silkscreen color and min text height/stroke

• Net‑tie, slots, depth routes, back‑drill, controlled depth notes if used; padstack definitions for microvias and teardrops

• Panelization: array, rails, tooling holes, fiducials, coupon location, break‑off style

• RoHS/REACH compliance requirement and any restricted substance declarations

How HyperPCB engages on quotes and quality

• ISO 9001:2015 certified QMS (certificate no. CN-2023-Q1156, SGS, valid until June 2027).

• Quotes returned within 24 hours and DFM feedback within 1 business day.

• Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria.

• RoHS and REACH compliance is supported for hazardous substance control.

• Our partner factory AEGIS maintains ISO 9001/14001/45001 and additionally ISO 13485 and IATF 16949 when your program needs those frameworks, and manufactures high‑frequency laminates used by RF PCB fabricators in China.

If your design targets a specific impedance or RF laminate family, send the target Dk/Df and layer map with your Gerbers so we can lock the stack and coupon design up front.