How to connect same-type pins (e.g., VCC_3V3) in schematics

Short answer

Give all same-type power pins the same net name (e.g., VCC_3V3), connect them with explicit net labels or power symbols, and implement the connection on the PCB with a solid plane and per-pin decoupling. Avoid daisy-chaining IC power pins; use the plane as the common node.

Name one rail, everywhere

Pick a canonical rail name (3V3, VCC_3V3, or +3V3) and use it consistently across the design. Prefer explicit net labels or power ports over relying on hidden power pins. If a symbol comes with hidden VCC, unhide and connect it so the schematic shows the intent.

Should I use global power symbols or local labels?

Both are valid. Global power symbols make the rail visible across sheets automatically; local net labels keep scope explicit in hierarchical designs. If you use local labels per sheet, add hierarchical connectors/off-sheet connectors so the rail is truly one net through the hierarchy. Don’t mix 3V3, VCC, and +3V3 unless you deliberately alias them in the tool—most tools treat different strings as different nets.

Multiple VCC pins on one IC

Tie all power pins of an IC to the same rail. Give each power pin a local 0.1 µF (100 nF) ceramic to the closest ground, placed within 2–3 mm of the pin, and add 1 µF per device and 4.7–10 µF bulk per rail region. Use short, wide traces to the plane, or via-in-pad for BGAs. Avoid daisy-chaining from cap to cap; each cap should see the plane with its own short path to minimize loop inductance.

Can I connect two sources to the same rail?

Only if one is the source and the others are sinks. Power_out to power_out direct ties (e.g., two regulators to 3V3) are generally not acceptable and will be flagged by ERC. If you must combine sources, use OR-ing (Schottky diodes with ~0.2–0.4 V drop) or an ideal-diode controller. If a net has only power_in pins, add a power-flag/power-net marker so ERC knows it is driven.

When to use a net tie or ferrite bead?

Use a net tie part to deliberately connect two named nets at a defined, single point (e.g., AGND to GND). For cleaning digital noise on an analog 3V3_A rail, a ferrite bead (often ~600 Ω at 100 MHz, DC resistance <100 mΩ) between 3V3 and 3V3_A is common. Place bead near the split point, with local decoupling on the quiet side. Keep currents realistic; beads saturate.

ERC/DRC practices that prevent surprises

• Mark the rail as driven if your tool requires a power flag.

• Set pin types correctly: regulators as power_out, IC VDD pins as power_in, beads as passive.

• For hierarchical designs, verify that 3V3 passes between sheets via defined connectors.

• Run ERC early so mistaken net names (3V3 vs 3v3) are caught.

PCB layout makes the connection real

Use a continuous power plane for 3V3 to minimize impedance. Give each IC a short via pair (power and ground) near its decouplers. For rails carrying >0.5–1 A, add multiple stitching vias where the rail transitions layers. Size any trace segments to current per IPC-2152; as a ballpark, an external 1 oz copper trace carrying 1 A with ~10 °C rise is on the order of 0.5–1.0 mm wide, but verify with your stackup and environment. Keep return paths short and unbroken.

Duplicated connector pins on the same rail

If a connector exposes multiple 3V3 pins for current sharing, tie them together on the PCB with a short copper bar/plane near the connector so the current divides, and route adequately wide traces from that node. Don’t rely on two distant joins elsewhere on the board to equalize current.

Naming and documentation that scale

Document rail purposes: 3V3 (digital), 3V3_A (analog), 3V3_RTC (always-on). Use net classes to control width/clearance by rail. Add test points on each rail segment for bring-up.

Quick checklist

• One canonical net name per rail across all sheets.

• Use power symbols or explicit labels consistently, not both ad hoc.

• Every IC power pin: its own 100 nF, shortest path to ground and plane.

• No power_out-to-power_out ties without OR-ing.

• Use net ties/ferrite beads for intentional, single-point connections.

• Verify with ERC/DRC; fix scope and naming issues early.

• Size copper per IPC-2152 and verify PDN impedance versus load.

Why this matters for fabrication

Clear, unambiguous power nets reduce fab and test risk. Boards at HyperPCB can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria, and we support RoHS and REACH compliance. Our quality management system is ISO 9001:2015 certified (certificate CN-2023-Q1156, SGS, valid to June 2027).