How to continue a differential pair ground reference from PCB to cable

Use a shielded twisted pair (twinax) and bond the shield 360° to chassis at the connector; let the two conductors remain tightly coupled so the pair self-references, while the shield provides a low-impedance path for common-mode current—do not insert a ground wire between the two lines.

What is the ground reference in a cable?

On a PCB, a differential pair’s image/return current flows in the adjacent reference plane under each trace. In a cable there is no plane; the two conductors reference each other, and any imbalance or external fields create common-mode current that returns on the cable shield (if present) or on nearby conductors. Your job is to keep the two signal conductors tightly coupled and give common-mode current a short, broadband return via the shield and chassis.

Choose the right cable and impedance

Pick a cable whose differential impedance matches your interface within typical ±10%: 90 Ω (USB 2.0), 85 Ω (USB 3.x, PCIe), 100 Ω (LVDS, Ethernet). Use shielded twisted pair or twinax; for multi‑Gb/s, individually foil‑shielded pairs with a drain wire plus an overall braid lower EMI and crosstalk. Keep pair twist intact to the contacts; avoid untwist > 10 mm at terminations.

How should I terminate the shield?

Use a full 360° shield termination to chassis at the connector (metal backshell, clamp, or spring fingers to a chassis ring). Avoid pigtails; if unavoidable, keep them < 10 mm. For EMI/ESD control, many designs bond the shield directly to chassis at the I/O end and capacitively (for example, 1–4.7 nF to chassis or case ground) at the far end to shunt RF while limiting low‑frequency ground loops. Place ESD/TVS to chassis right at the connector.

Connector and pinout to preserve the pair

Map the two signals onto immediately adjacent pins through the connector and into the cable. Do not place a ground pin or wire between the two signals, which increases differential impedance and mode conversion. Flank the pair with ground pins or shells instead, and keep the pair’s spacing and reference consistent across the transition. For multi‑Gb/s links, target intra‑pair skew < ~10 ps (≈2 mm in typical cable with vp ≈ 0.66c).

Pinout and termination do/don’ts

• Do: adjacent signal pins for the pair; ground/shield surrounding, not in between

• Do: maintain pair spacing and keep stubs/untwist short (< 10 mm)

• Do: 360° shield bond to chassis; add a common‑mode choke near the connector when needed (e.g., 90–120 Ω CM @ 100 MHz)

• Don’t: route one leg over a different reference or add a separate ground wire between the signals

• Don’t: change pair spacing at the connector without re‑validating impedance

Controlling the transition off the PCB

Keep the pair on a continuous reference plane up to the connector; use stitching vias to maintain the return path around any slot or cutout. If the connector forces a layer change, use tightly coupled vias and minimize via count. Avoid stubs and keep anti‑pads sized to preserve impedance. Place the common‑mode choke (if used) and ESD close to the connector to intercept noise before it hits the cable.

What if there’s no shield in the harness?

Then include a dedicated ground conductor adjacent to (but not between) the two signal wires and bond it to board ground at both ends. Expect higher emissions and susceptibility versus a shielded pair; keep runs short and consider ferrites/CM chokes on entry.

Validation and sign‑off

Verify with TDR that the differential impedance through pads, connector, and cable stays near 85/90/100 Ω as required. Check S‑parameters for return loss and mode conversion (Sdd11, Sdc21). In the lab, probe for common‑mode currents on the shield with a clamp and check radiated scans; excessive CM current usually points to poor shield bonding or asymmetry in the transition.

Notes on stack‑ups and calculators

Use a field solver for PCB launch geometry; IPC‑2141 equations are acceptable for first‑pass estimates but can miss edge effects at connectors. Keep the launch geometry and pad fields symmetric so the pair sees the same parasitics on both legs.

Procurement and compliance considerations

If you need fabrication to defined acceptance criteria and substance control, boards can be built and inspected to IPC Class 2 or Class 3 acceptance criteria, and RoHS/REACH compliance is supported. HyperPCB operates an ISO 9001:2015 certified quality management system (certificate no. CN-2023-Q1156, issued by SGS, valid until June 2027). Quotes are returned within 24 hours and DFM feedback is provided within 1 business day.