How to design an HDI PCB stackup: layers, microvias, impedance

Fast path to a workable HDI stackup

For 0.35–0.50 mm BGAs, use Type II–III build-ups with 50–75 µm RCC, 0.10 mm laser microvias (aspect ≤1:1), and size 50 Ω outer microstrip ≈100–120 µm on h≈60 µm (Dk≈3.4); confirm with a field solver and lock lamination cycles early to protect yield.

What is an HDI stackup?

An HDI stackup adds one or more thin build-up dielectric/copper layers to a core and uses laser microvias for dense escapes. Typical build-up dielectrics are 50–100 µm per layer with 9–18 µm copper. Laser microvias are ~75–100 µm drill with capture pads ~0.25–0.35 mm. Designs mix through-holes in the core, buried vias, and blind microvias (e.g., L1→L2) with stacked or staggered options.

Which HDI type fits 0.35–0.5 mm BGAs?

Type I (single build-up, no buried vias) works when BGA pitch is ≥0.50 mm and total layers stay modest. If you must break out 0.40–0.50 mm BGAs while limiting through-hole congestion, Type II (build-up plus buried vias in the core) is efficient. For 0.30–0.35 mm BGAs or tight z-height control, Type III (two or more build-ups per side, stacked/staggered microvias) becomes practical. Each additional build-up adds a lamination cycle; plan the count up front.

Microvia geometry, pads, and stacking limits

Keep microvia aspect ratio ≤1:1 (dielectric thickness to laser hole). Common stacks use 50–75 µm dielectrics with 75–100 µm drills. Provide ≥25–50 µm capture annular ring on the target layer; 0.25–0.30 mm pad fits 0.10 mm microvias well. Via-in-pad under fine-pitch BGAs is routine; use resin fill for single blind microvias with low current, and copper fill where stacking or planarity/current demand it. Cap plating ~20–25 µm over copper-filled vias provides robustness. Prefer staggered stacks; if stacking, keep to two-high unless the base is copper-filled and proven in reliability testing.

How to hit 50 Ω and 90/100 Ω in thin dielectrics?

Use a field solver (IPC-2141 analytical forms are a check, not the final word) with actual copper after plating and a realistic Dk. Typical results: with Dk≈3.4, outer microstrip h=60 µm, Cu=12 µm, 50 Ω width ≈100–120 µm. For 100 Ω differential on the same layer, width ≈70–80 µm with edge-to-edge spacing ≈90–110 µm; 90 Ω differential (USB HS/MIPI) often lands near w≈60–70 µm, s≈70–90 µm on 50–60 µm microstrip dielectrics. For inner stripline targeting 100 Ω with Dk≈3.6 and plane separations ≈70 µm above and below, Cu=12 µm, single-ended width ≈60 µm and differential spacing ≈80 µm are common. Account for etch factor and plating growth; a ±10% impedance tolerance is typical unless otherwise negotiated.

Materials for build-ups and cores

Build-ups commonly use RCC or very thin prepregs to reach 50–100 µm per dielectric. FR-4 class materials show Dk≈3.5–3.8 @ 1 GHz; low-loss options (Dk≈3.2–3.3) help 10+ GHz links and reduce width for a given impedance. Useful prepreg references (post-lam thickness): 106 ≈50–65 µm, 1080 ≈80–100 µm, 2116 ≈110–130 µm, 7628 ≈180–200 µm. Build-up copper is typically 9–18 µm; cores carry 18–35 µm before outer-layer plating.

Warpage control and lamination planning

Symmetry matters: mirror the build-up above and below the core when possible to control bow/twist. Keep per-layer copper balance within roughly 10–15%; add thieving where planes are sparse. Minimize lamination cycles by consolidating buried-via steps in the core rather than adding extra build-ups.

Clearance, mask, and manufacturable rules

Practical HDI geometry often targets 75/75 µm (3/3 mil) trace/space in build-ups and 100/100 µm (4/4 mil) in the core. Maintain microvia-to-copper (non-pad) clearances of ≥100–125 µm. Solder mask dams between pads should be ≥75–100 µm. Keep through-hole aspect ratio to ≤8–10:1 for robust yields.

What do fabricators need to quote and build?

• Target impedances and tolerances (e.g., 50 Ω ±10%, 100 Ω ±10%)

• Full stack table: each dielectric thickness and copper weight (pre/post plate if known)

• Via scheme: which layers, stacked or staggered, and fill type (resin or copper)

• Controlled impedance layer/pair assignments and test coupon requirements

• Net classes with line/space and any microvia keepouts/antipads

Example stackups you can adapt

Type II, 8L: symmetric single build-ups (12 µm Cu over ~60 µm dielectrics) on a core with buried vias (e.g., L3↔L6 at 0.20–0.25 mm mechanical). Use L1→L2 and L8→L7 microvias at 0.10 mm. Route 90 Ω differential on L1 with w≈70 µm, s≈90 µm; 100 Ω differential stripline on L4/L5 with w≈60 µm, s≈80 µm when plane-to-trace dielectrics are 70–90 µm.

Type III, 10L: two build-ups per side (≈50 µm each), stacked L1→L2→L3 and L10→L9→L8 microvias (copper-filled in via-in-pad under 0.35 mm BGA). Place 100 Ω differential SERDES on inner striplines using low-loss build-up (Dk≈3.2); w≈55–65 µm, s≈70–85 µm is a frequent solution space.

DFM checkpoints and quoting timeline

Before layout freeze, verify microvia aspect ratios, capture rings, copper coverage over pads, and antipads for stacked vias; check copper balance and lamination count with your fabricator. Quotes are typically returned within 24 hours and DFM feedback within 1 business day, which makes stackup iteration practical prior to release.

Standards, acceptance, and compliance options

Use IPC-2226 for HDI design rules and IPC-6012/6016 for performance and acceptance. Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria, and RoHS/REACH compliance is supported. HyperPCB operates under an ISO 9001:2015 certified QMS (certificate CN-2023-Q1156, issued by SGS, valid until June 2027).