How to get a reliable PCB quote from your Gerber files

You get a reliable PCB quote by sending a complete, unambiguous Gerber/drill set plus a fab drawing that fixes stackup, tolerances, and test.

Quote‑ready Gerber package checklist?

• RS‑274X layers: copper (outer/inner), solder mask, silkscreen, and a mechanical outline with finished dimensions

• Excellon drills: tool table, units, coordinate format, and a drill map

• Fabrication notes: finished thickness (e.g., 1.60 mm), layer count, copper weights (e.g., 35 µm outer / 18 µm inner), surface finish (HASL or ENIG), mask/legend colors, IPC acceptance class per IPC‑6012, key tolerances, countersink/counterbore callouts

• Stackup table: dielectric materials and thicknesses (e.g., FR‑4 Tg 150; 7628 or 2116 prepregs; core thicknesses)

• Impedance table: targets (e.g., 50 Ω single‑ended, 90 Ω differential) and tolerance (±10% unless tighter)

• Optional IPC‑356A netlist for test planning

• Panelization: array size, rails ~10 mm, and global fiducials ~1.0 mm if needed

• Readme: contact, quantities and breaks, ship‑to, and any special processes (via‑in‑pad, blind/buried, edge plating)

How do fabricators read cost drivers from Gerbers?

From your data we extract panel utilization, layer count, minimum trace/space, finished hole sizes and aspect ratio, via types, copper weights, finishes, solder‑mask requirements, and test. Concrete thresholds that often move a quote into a different process window:

• Panel utilization: On a 457 × 610 mm panel with 10 mm rails each side, a 100 × 100 mm board fits floor((457−20)/100) × floor((610−20)/100) = 4 × 5 = 20 pcs/panel. A 102 × 102 mm outline drops to 3 × 5 = 15 pcs/panel, raising cost per piece despite similar area.

• Trace/space: ≤0.10 mm (4 mil) typically requires tighter imaging and etch control; ≤0.075 mm (3 mil) may reduce yield further. With 2 oz (70 µm) copper, many shops push minimums to ≥0.15 mm due to etch undercut.

• Finished hole: ≤0.20 mm needs micro‑drilling; for a 1.60 mm board that’s an 8:1 aspect ratio (finished), already a plating limit in many lines. ≤0.15 mm finished often implies laser or special drills.

• Blind/buried vias: Any L1–L2 or L(n−1)–Ln blind via adds at least one extra lamination and drill cycle; stacked microvias add via‑fill and planarization steps.

• Finish: ENIG adds nickel/gold deposition (Ni ~3–6 µm, Au ~0.05–0.10 µm) over copper; more steps than HASL and typically priced higher.

• Solder mask: Dam width <0.10 mm between pads risks solder bridging; mask‑defined pads and tight clearances require fine LPI processing.

• Copper‑to‑edge: <0.30 mm to routed edge invites burrs/exposure; add pull‑backs or edge plating as needed, both changing cost.

• Drill density: Very high hit counts (e.g., >80,000 hits/m²) extend spindle time and tool wear, impacting unit cost.

Clear, quantified notes prevent conservative assumptions (e.g., defaulting to ENIG or HDI) that inflate a quote.

Two concrete quote scenarios

• Four‑layer, 100 × 100 mm, 1.60 mm board, 0.15/0.15 mm rules, 0.30 mm finished PTH, 1 oz Cu, HASL, no controlled impedance: one lamination cycle, one drill cycle, 20‑up per 457 × 610 mm panel after 10 mm rails.

• Same outline but 0.09/0.09 mm, 0.20 mm finished PTH, ENIG, and 50 Ω/90 Ω impedance on outer layers: micro‑drilling, tighter imaging, ENIG line, impedance documentation and image scaling. More process steps, potentially fewer panels passing first‑time yield, so a higher quote for the same outline.

Controlled impedance from Gerbers — what to state

Put the target, tolerance, and layer locations in your fab notes. Example: “L1 microstrip 50 Ω ±10% over FR‑4, Dk 3.8–3.9; L2 is reference plane; L1–L2 dielectric 0.18 mm; outer Cu 35 µm; inner Cu 18 µm.” On that geometry, a 50 Ω microstrip is typically ~0.20–0.24 mm wide; a 90 Ω differential pair often uses ~0.10–0.12 mm lines with ~0.10–0.12 mm gap. If you don’t know exact dielectric, specify acceptable prepreg families (e.g., 2116/1080 or 7628 where thickness allows) and tolerance. The fabricator will tune the image to hit Z0 and report the built stackup.

No stackup yet — can you still get quoted?

Yes. State finished thickness (e.g., 1.60 mm), target impedances and tolerances, outer/inner copper weights, and any material constraints (FR‑4 Tg class or Dk range). You’ll receive a proposed stackup to lock in on the fab drawing before PO.

What DFM checks should you expect?

Expect calls on annular ring (aim ≥0.10 mm), aspect ratio (≤8:1 for standard PTH on 1.60 mm), solder‑mask slivers (<0.10 mm flagged), legend‑to‑pad clearance, copper thieving for plating balance, copper‑to‑edge (≥0.30 mm), and impedance feasibility versus stated dielectric/copper. Test strategy is typically flying‑probe for prototypes and fixture for stable, higher‑volume designs.

Compliance and response times

Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria. RoHS and REACH compliance is supported for hazardous substance control. Our quality management system is ISO 9001:2015 certified (certificate CN‑2023‑Q1156, issued by SGS, valid until June 2027). Quotes are returned within 24 hours and DFM feedback within 1 business day.

Pre‑submit verification

Open the Gerbers and drills in a neutral viewer, confirm units and coordinate formats, ensure the outline exists on a mechanical layer, and that fab notes list finished (not tool) hole sizes. Zip with a clear revision tag to avoid re‑quotes for mismatched data.