How to locate signal distortion on a high‑speed PCB

To locate signal distortion on a high‑speed PCB, combine TDR/TDT and VNA time‑domain gating to pinpoint discontinuities, near‑field scanning to find crosstalk hotspots, and eye/S‑parameter analysis to rank what actually degrades margin.

Instruments that actually locate distortion

• TDR/TDT or a VNA with time‑domain transform to map reflections and insertion loss vs distance

• High‑bandwidth scope with differential probes for eye and step response at pins

• Near‑field E/H probes and a spectrum analyzer to scan for radiators and aggressors

• SERDES diagnostics (eye/BER/CTLE/DFE telemetry) to correlate channel fixes with margin

How do I turn TDR time into board distance?

A TDR measures round‑trip time to a discontinuity. Location x ≈ vp·t/2, where vp = c/√εeff. For FR‑4 microstrip, εeff ≈ 2.8–3.2, vp ≈ 1.7–1.8×10^8 m/s. Example: a 100 ps reflection corresponds to about 8.5–9 mm from the launch. Spatial resolution is Δx ≈ vp·Δt/2; with 50 ps resolution you can separate features ∼4–5 mm apart on FR‑4 microstrip.

Reflections to hunt and how big they are

Any impedance step Z1→Z2 causes Γ = (Z2−Z1)/(Z2+Z1). A 50→40 Ω neck‑down gives Γ ≈ −0.111 (−19 dB); a 50→60 Ω step gives +0.091 (−20.8 dB). Look for: connector launches, via fields (antipad/capture pad size), pair neck‑downs at BGA escapes, plane splits at layer swaps, stubs from unused vias, skewed pair geometries, meanders close to ground voids. Differential: watch for mode conversion (Sd21) when pair symmetry breaks, e.g., unequal antipads or one trace crossing a split.

Can I separate loss from via‑stub resonances?

Loss is broadband; stubs create narrow notches. Via‑stub quarter‑wave resonance is f0 ≈ c/[4·√εr·Lstub]. A 1.6 mm stub in εr ≈ 4 resonates near 23 GHz; harmonics appear at odd multiples. Use backdrill or blind/buried vias when any resonance approaches your significant spectral content (fundamental and a few harmonics; a 10 Gb/s NRZ channel needs margin well past 10 GHz). Copper roughness and dielectric loss dominate above a few GHz; choose low‑profile copper and lower‑Df cores for long links.

Crosstalk: where does it originate and how to localize?

NEXT often spikes near the transmitter breakout; FEXT accumulates with length. With a VNA, examine S31/S41 for aggressor→victim coupling; time‑gate to specific regions. With a near‑field probe, scan along parallel runs, connector breakouts, and layer changes; crosstalk hotspots align with tight spacing, long broadside overlaps, or reference plane changes without return vias. Rule‑of‑thumb spacing: ≥3W for microstrip to keep coupled noise roughly below −30 dB over short runs; add ground via fences near edge‑coupled pairs and board edges.

Power integrity that looks like SI—how to tell?

Broadband jitter or deterministic periodic jitter at switcher frequencies points to PDN noise. Check supply rails with a low‑noise probe at the receiver; look for spur families (e.g., 500 kHz, harmonics). Inject a step on the rail and observe package+PDN impedance; target flat Z across your data spectral band to reduce supply‑induced jitter.

Stackup and layout checks that prevent hotspots

• Keep reference plane continuity under every high‑speed segment; never cross a split. If you must change reference layers, place stitching capacitors and return vias within a few mm of the transition.

• Control impedance: 50 Ω single‑ended, 90 Ω diff (USB 3.x), 100 Ω diff (Ethernet, PCIe) are typical; verify with a 2‑D field solver and include plating/etch bias.

• Minimize via count; tune antipads and pad stacks; backdrill unused via barrels on multi‑gigabit lanes.

• Maintain pair symmetry through connectors and vias; avoid unequal neck‑downs; match intra‑pair within a few ps (FR‑4 delay ~140–170 ps/in, ~5.5–6.7 ps/mm).

• Mitigate weave skew: prefer spread‑glass or mixed glass styles; route pairs at small angles or with periodic swaps to average fiber exposure.

What should I specify to manufacturing?

Provide the target impedances and tolerances (e.g., 50 Ω ±10%, 100 Ω ±10% or tighter for multi‑Gb/s), full stackup with core/prepreg styles (e.g., include 7628 vs 2116 usage), finished copper, plating, and soldermask. For low loss, request low‑profile or very‑low‑profile copper (Ra ≲ 2 μm) and laminate Dk/Df at your band of interest. Call out controlled‑depth backdrill on lanes requiring it. State acceptance to IPC Class 2 or Class 3 as needed, and require RoHS/REACH compliance.

When lab gear is limited, what can I do?

Use scope‑based TDR/TDT fixtures for coarse localization, then validate with loopback eye tests using the device’s internal PRBS/BER counters or eye telemetry. Toggle aggressor nets to correlate victim degradation. Insert targeted fixes (e.g., add return vias near a layer change) and re‑measure deltas to converge on the culprit.

About HyperPCB manufacturing and support

HyperPCB operates an ISO 9001:2015 certified quality management system (certificate CN‑2023‑Q1156, SGS, valid to June 2027). Quotes are returned within 24 hours and DFM feedback within 1 business day. Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria, and RoHS and REACH compliance is supported. Our partner factory AEGIS maintains ISO 9001:2015, ISO 14001:2015, ISO 45001:2018, ISO 13485:2016, and IATF 16949 management systems, and manufactures its own high‑frequency laminates supplied to RF PCB fabricators in China, including publicly listed PCB companies. These controls matter directly to high‑speed performance because impedance, loss, and via quality hinge on stackup accuracy, material control, and drilling/backdrill precision.

Field workflow that finds problems fast

1) Calibrate VNA or TDR, measure S11/S21 and TDR. 2) Time‑gate to isolate connectors and via fields; convert peaks to position. 3) Scan with a near‑field probe over the gated region. 4) Implement the smallest physical change that theory suggests (e.g., add a stitching via, remove a stub) and re‑measure. 5) Lock fixes in the stackup and fabrication notes before build release.