How to select CN3791 charger inductor, sense resistor, MPPT, and capacitors

Size CN3791 solar‑charger parts by fixing battery float voltage and MPPT setpoint first, then computing inductor L from buck equations and charge‑current sense Rs from the datasheet sense threshold; below are concrete numbers and part examples.

What changes drive CN3791 component values?

Battery chemistry (per‑cell float/termination), panel open‑circuit voltage Voc and temperature, target charge current Ichg, and whether the power stage is synchronous or uses a Schottky. With those fixed, you can compute MPPT voltage (≈0.70–0.80 Voc; 0.73 × Voc is a good start), inductor ripple, cap ripple, and thermal loss budget.

Battery chemistry and float voltage choices

Pick float first; it drives duty cycle and power loss. Typical per‑cell values engineers actually use: Li‑ion 4.20 V ±1% (variants 4.10–4.35 V; follow cell datasheet), LiFePO4 3.60–3.65 V, lead‑acid absorb ≈2.40–2.45 V/cell then float ≈2.25–2.30 V/cell. If the CN3791 uses a resistor divider for float, compute R ratio from its Vref per the datasheet; add a pack NTC (10 kΩ, B ≈ 3435 K) to gate charging over temperature.

How to set MPPT from panel Voc?

Measure Voc over your temperature/irradiance range. Start Vmppt at ≈0.73 × Voc (crystalline Si norm), then verify on a programmable load while logging I×V in sun and with a solar simulator. Set the input UVLO a bit below Vmppt so the buck does not chatter at dawn/dusk. RC‑filter the MPPT sense node (for example, tens of kΩ and tens of nF) to tame switch ripple.

Inductor sizing with worked examples

Use L ≈ Vout × (1 − Vout/Vin) / (ΔIL × f_sw), with ΔIL = k × Ichg and k ≈ 0.2–0.4. Example A (1‑cell Li‑ion): Vout 4.20 V, Ichg 2.0 A, panel at MPPT Vin 18 V, f_sw 300 kHz (use the actual CN3791 value), k 0.3 → ΔIL 0.6 A → L ≈ 4.2 × (1 − 4.2/18) / (0.6 × 300 kHz) ≈ 17.9 µH → pick 18 µH. Isat ≥ Ichg + ΔIL/2 ≈ 2.3 A; lower DCR reduces I²R loss. Example B (12 V SLA absorb 14.4 V, Ichg 5.0 A, 60‑cell panel Vmppt 30 V, same f_sw and k): ΔIL 1.5 A → L ≈ 14.4 × (1 − 14.4/30) / (1.5 × 300 kHz) ≈ 16.6 µH → pick 15–18 µH with Isat ≥ 5.75 A.

Sense resistor, diode, and thermal checks

Set constant‑current with Rsense = Vcs/Ichg (use the CN3791 datasheet Vcs). Example A with Vcs = 100 mV → Rsense 0.05 Ω, P ≈ 2.0² × 0.05 = 0.20 W; use ≥0.5–1 W metal‑element and Kelvin trace to the IC pins. Example B (5 A) with Vcs = 100 mV → Rsense 0.02 Ω, P ≈ 0.50 W; use ≥2 W and keep copper for heat spreading. Non‑synchronous buck diode loss ≈ Ichg × Vf × (1 − D), D ≈ Vout/Vin. Example A: D ≈ 0.233; at Vf ≈ 0.45 V, Pdiode ≈ 0.69 W. Check junction rise with θJA and board copper; upsize package or heatsink if needed.

Capacitors and expected ripple

Buck input RMS ripple current ≈ Ichg × sqrt(D × (1 − D)). Example A: 2 A × sqrt(0.233 × 0.767) ≈ 0.85 A; Example B: 5 A × sqrt(0.48 × 0.52) ≈ 2.5 A. Combine MLCCs close to the switch with polymer/electrolytic bulk rated for that ripple at 105 °C. To limit input droop ΔVin, Cin ≳ Ichg × D × (1 − D) / (f_sw × ΔVin). Output capacitive ripple ≈ ΔIL / (8 × f_sw × Cout). Example A with ΔIL 0.6 A, f_sw 300 kHz, Cout 44 µF MLCC → ΔV_C ≈ 5–6 mV (ESR adds linearly: ESR × ΔIL). Parallel MLCCs to reduce ESR and temperature derating.

Layout, protection, and test points

Minimize the high‑di/dt loop (IC switch, diode/MOSFET, input MLCC, return). Place the inductor at the switch node, pour copper under hot parts, and stitch thermal vias. Kelvin route Rsense. Add a TVS at the panel connector: for ≈18 V Vmppt use a 24 V standoff SMA/SMB device; for ≈30 V Vmppt use ≈33 V standoff. Add reverse‑polarity protection (series Schottky or ideal‑diode MOSFET). For 12–30 V DC, keep ≳1.0 mm creepage around the panel input and slot if contamination is expected. Bring out test pads for MPPT node, Rsense Kelvin, and battery node to speed validation.

Example reference BOM (per the two examples above)

• Inductor: Coilcraft XAL7030‑183 (18 µH, Isat 6.5 A, 12 mΩ DCR) for 2 A; Bourns SRP7050TA‑150M (15 µH, Isat 10 A) for 5 A

• Sense resistor: Vishay WSL2512 0.05 Ω 1 W (2 A case); Stackpole CSS2H‑3920R‑L100F 0.02 Ω 2 W (5 A case)

• Diode (non‑sync): Vishay SS34 (3 A, 40 V) for 18 V input; Diodes Inc. B560C‑13‑F (5 A, 60 V) for 30 V input

• Input caps: 2× Murata 22 µF 50 V X7R (GRM32ER71H226KE15) near switch plus Panasonic FR 100 µF 50 V bulk

• Output caps: 2× 22 µF 16 V X7R (1‑cell) or 2× 22 µF 25 V X7R (14.4 V SLA)

• TVS at panel: SMBJ24A for ≈18 V Vmppt; SMBJ33A for ≈30 V Vmppt

• NTC: Semitec 103AT‑2 10 kΩ placed on the pack; route to CN3791 NTC input

Build and compliance at HyperPCB

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