ICM-42688-P/PC no SPI response: hardware and firmware checklist

If your ICM-42688-P/PC shows no SPI response, verify interface mode, power, pin strapping, and confirm a WHO_AM_I read at 0x75 before anything else.

Quick pass/fail: WHO_AM_I over SPI

• With CS low, send an address byte 0xF5 (0x75 with read bit = 1), then clock one dummy byte (0x00). Read MISO on the second byte. Expect 0x47. If you don’t see 0x47, treat it as a link-level issue (power, mode, wiring, timing).

Is the device really in SPI mode?

• CS must be actively driven. If CS stays high, many InvenSense parts default to I2C and ignore SPI.

• Do not strap SDO/AD0 to GND or VDD. In SPI it is MISO; tying it bricks the MISO line. If you previously used I2C, remove the hard strap and, if needed, use a 10 kΩ resistor to bias during bring-up.

• Leave only one master enabled. If another device or level shifter holds CS/MOSI/SCLK, the IMU won’t see valid frames.

Power, reset, and the first 50 ms

• Verify VDD and VDDIO are within the datasheet ranges and match your host I/O voltage; mismatched VDDIO often looks like a dead SPI.

• Decouple VDD and VDDIO locally (100 nF close to pins, plus 1 µF bulk). Poor decoupling can corrupt early transactions.

• After power-up, delay at least 50 ms before the first SPI access. If unsure, use 100 ms during bring-up.

• If you can talk later, issue a software reset (then re-wait) to clear bad states.

What SPI mode and frame work?

• Use 4‑wire SPI, 8‑bit frames, MSB first.

• Start with SPI Mode 0 (CPOL=0, CPHA=0). If no joy, try Mode 3 (CPOL=1, CPHA=1). Many IMUs accept either 0 or 3; other modes will fail silently.

• Keep SCLK conservative first (≤1 MHz) and lengthen CS low time to cover both bytes of a read (address, then dummy/data).

Wiring traps that kill MISO

• MOSI/MISO swapped or SCLK/CS crossovers on the PCB or cable.

• Series resistors too large on MISO/SCLK (try 22–33 Ω). Huge values blunt edges and break timing.

• Level shifters meant for open‑drain I2C on a push‑pull SPI line, or unidirectional parts on a bidirectional net.

• Shared MISO bus without proper tri‑state isolation; add a series 0 Ω option to isolate during debug.

How to probe with a logic analyzer?

• Check SCLK edges are clean and stable at your chosen mode.

• MOSI should show 0xF5 followed by 0x00 for a WHO_AM_I read.

• MISO should be high‑Z when CS is high, then return a stable 0x47 during the second byte.

• If MISO is stuck, lift SDO/AD0 from any straps and re‑check.

Register map sanity

• WHO_AM_I at 0x75 sits in the default bank; no bank select is required for this test.

• If WHO_AM_I works but other reads fail, confirm you are still in the correct bank when accessing motion registers.

PCB layout notes for stable SPI

• Keep SCLK and MOSI short and referenced to a continuous ground; avoid stubs on MISO.

• Place decouplers within a few millimeters of VDD/VDDIO pins with direct via-in-pad or short traces.

• If running off-board cabling, add 22–47 Ω series resistors on SCLK/MOSI near the master and consider a small RC (e.g., 33 Ω + 47 pF) on SCLK to tame ringing.

Manufacturing support for IMU bring-up

• We can build and inspect to IPC Class 2 or Class 3 acceptance criteria.

• RoHS and REACH compliance is supported.

• ISO 9001:2015 certified QMS (SGS, certificate CN-2023-Q1156) and quick turnarounds: quotes within 24 hours and DFM feedback within 1 business day.

Minimum reproducible test

• Power up, wait 100 ms, SPI Mode 0 at 1 MHz, CS low, send 0xF5 0x00, read MISO on the second byte. Expect 0x47. Only after this passes, raise SCLK and proceed to sensor configuration.