Is there a standard formula to size bulk caps for PWM loads?

There is no single standard formula; size the bulk capacitor with two checks: transient droop C >= (I_step * t_resp) / V_droop and PWM ripple C >= (I_pk * d) / (f_pwm * V_ripple), then verify ESR/ESL limits and the capacitor’s RMS ripple current rating.

What problem are we solving

Bulk capacitance at the source or rail holds the supply voltage within an allowed droop while a PWM load toggles current faster than the upstream source or regulator can respond. Define: I_step (A), f_pwm (Hz), duty d (0..1), allowed voltage droop V_droop (V), upstream loop/transport response time t_resp (s), and supply/trace impedance Z_s (ohms). The bulk cap supplies charge for the fast part; the regulator refills it more slowly.

How to size for load-step droop?

For the step from I1 to I2, use I_step = |I2 - I1| over the time before the source recovers t_resp (from datasheet or step-load test):

• Capacitance: C_min_transient >= (I_step * t_resp) / V_droop

• ESR limit (edge step): ESR_max = V_step_allow / I_step

• ESL/loop inductance (edge spike): V_spike ~ L_loop * (di/dt), so minimize L_loop with short, wide connections and multiple vias.

Example: I_step = 2 A, t_resp = 200 us, V_droop = 0.10 V -> C >= (2 * 200e-6) / 0.10 = 4.0e-3 F = 4,000 uF. If you can tolerate 200 mV droop, C halves to ~2,000 uF. If di/dt = 1 A/us and you allow <50 mV spike, L_loop must be <50 nH.

How to size for periodic PWM ripple?

If the upstream source cannot fully refill within one cycle, bound the worst-case droop during the on-time (conservative):

• Capacitance: C_min_pwm >= (I_pk * d) / (f_pwm * V_ripple)

• Cap RMS current (heating/stress): I_c_rms = I_pk * sqrt(d * (1 - d)) (peaks at d = 0.5 -> 0.5 * I_pk). Ensure I_c_rms is below the capacitor’s ripple current rating at temperature.

• ESR ripple at edges: V_esr_pp ~ I_edge_pk * ESR. Choose ESR to keep this within budget.

Example: I_pk = 2 A, f_pwm = 20 kHz, d = 0.5, V_ripple = 50 mV -> C >= (2 * 0.5) / (20e3 * 0.05) = 1.0e-3 F = 1,000 uF. I_c_rms at d=0.5 is 1 A.

PCB layout and component choices that matter

• Use a low-ESR bulk part (polymer electrolytic or aluminum polymer) to handle mA–kHz content, paralleled with MLCCs (e.g., 0.1–1 uF and 4.7–22 uF) to shunt MHz edges. MLCC DC-bias reduces effective C; for example, a 22 uF 6.3 V 0805 at ~5 V may deliver only a few uF.

• Keep the current loop between load, capacitor, and return as small as possible; loop inductance is roughly 0.5–1 nH per via and ~1 nH per few mm of narrow loop length. Place the bulk cap within a few millimeters of the switching load path and use multiple ground/power vias.

• The useful frequency range of a bulk capacitor is limited by ESR: f_esr ~ 1 / (2*pi*ESR*C). Above this, MLCCs dominate.

Quick sizing workflow

• Define budgets: V_droop_allow (step) and V_ripple_allow (periodic).

• Get I_step, f_pwm, duty d, and t_resp (datasheet or step test).

• Compute C_min_transient and C_min_pwm; choose C >= max of both.

• Check ESR_max = V_step_allow / I_step; pick parts with ESR below this.

• Verify I_c_rms = I_pk * sqrt(d * (1 - d)) versus capacitor ripple rating.

• Prototype and measure: step-load droop, edge spikes, and thermal rise on the capacitor body.

Is my current approach correct?

If you are calculating C from both transient (C >= I_step * t_resp / V_droop) and periodic ripple (C >= I_pk * d / (f_pwm * V_ripple)), and you separately constrain ESR, ESL (via di/dt), and I_c_rms, your approach matches standard engineering practice. If you used only one of these without checking ESR and ripple current, you risk under-sizing.

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