LT8625SPJV no VOUT: measurable checks, thresholds, and layout fixes

If LT8625SPJV VOUT is 0 V and PGOOD is low, the converter is not enabling or is held in protection; verify RUN/UVLO, SW activity, BST−SW bias, FB level, and output shorts with the numeric checks below.

What does 0 V at VOUT with PGOOD low imply?

PGOOD is open‑drain and stays low until the regulator reaches its feedback window. With VOUT at 0 V, first exclude a missing enable (RUN below threshold), insufficient VIN at the IC pins, a missing/incorrect bootstrap cap, a miswired feedback divider, or a hard short on VOUT.

Fast numeric checks on the bench

• VIN at the IC pins: probe VIN to PGND right at the package. During the first milliseconds of start‑up, keep VIN at least 0.5–1.0 V above your UVLO setpoint (or any external supply margin) without droop.

• RUN threshold: scope RUN; it must cross ≈1.0 V cleanly (typical enable for this family) and remain high. If you use a UVLO divider, confirm resistor values and orientation.

• SW node: with VIN present and RUN high, SW should toggle between ~0 V and ~VIN at the chosen fSW. SW stuck at 0 V points to RUN/UVLO/thermal/boot issues; SW stuck at VIN suggests a shorted high‑side or FB commanding 100% duty into a heavy short.

• BST−SW bias: measure V(BST)−V(SW); when switching, expect roughly 3–5 V of gate‑drive bias. ≈0 V here means the high‑side cannot be driven (missing/incorrect 0.1 µF X7R from BST to SW, wrong orientation, or broken connection).

• FB pin: in regulation FB ≈ 0.97 V (typical for this LT86xx family). If FB ≈ 0 V with no SW activity, FB may be shorted to GND; if FB >> 0.97 V, look for leakage/misplaced feed‑forward from VOUT to FB.

• Inductor continuity: DCR should be tens of mΩ; a near‑open inductor yields 0 V at VOUT even if SW is switching.

• Output short check: with power off, VOUT‑to‑GND resistance should be well above a few kΩ on an unloaded board; <1 Ω indicates a short/solder bridge/reversed cap.

• PGOOD wiring: add a 10–100 kΩ pull‑up to a valid logic rail; left floating, PGOOD may read low regardless of regulation.

RUN/UVLO and sequencing details

If RUN is driven by another rail, scope VIN and RUN together. Slow or chatter‑prone RUN can repeatedly arm/disarm the controller. Set the UVLO divider so RUN crosses the enable threshold after the input ceramics at VIN have charged; a 0.5–1.0 V VIN margin above the RUN threshold at the IC pins is a practical target. Remove external loads and start with a resistive load equivalent to 100–500 mA to avoid pre‑bias or heavy inrush interactions.

Is the feedback network correct?

Use VOUT = VREF × (1 + Rtop/Rbot) with VREF ≈ 0.97 V (check your datasheet revision). Size the divider for 10–50 µA through Rbot to balance noise and loading. Example for 5.0 V: Rbot ≈ 100 kΩ, Rtop ≈ 412–422 kΩ. Swapped divider legs will park VOUT near VREF (~1 V). In regulation, FB should read near VREF; large deviation means the loop is not in control.

Bootstrap and switching sanity

Fit a 0.1 µF X7R from BST to SW placed adjacent to the pins; long traces starve the gate driver. During operation, V(BST)−V(SW) of roughly 3–5 V confirms the high‑side gate drive is biased. Add a small 1–4.7 µF ceramic directly from VOUT to GND at the IC pins to keep ESL low during start‑up.

Layout pitfalls that suppress start‑up

Minimize the hot loop (VIN ceramics → high‑side switch → SW node → catch path → PGND); place multiple X7R input capacitors within a few millimeters of the VIN/PGND pins to limit ringing that can trip UVLO/OVP. Route FB as a Kelvin sense from the filtered output after the inductor, away from SW, and return the bottom divider resistor to a quiet analog ground—not the high‑current PGND pour. Keep the BST cap loop tiny.

What scope captures isolate the root cause?

Record VIN, RUN, SW, BST−SW, VOUT, and FB on the same start‑up, with timebase covering the first 2–5 ms. These six traces reveal whether the controller enables (RUN), attempts to switch (SW), has bootstrap bias (BST−SW), reaches the reference (FB), and transfers energy to the output (VOUT) without being dragged down by a short or overload.

Fabrication notes for high‑current bucks

Use generous copper in the hot loop and ground returns; 2 oz copper or local copper pours reduce loss and temperature rise. Where thermal or current density is critical, via‑in‑pad (filled and capped) improves vertical heat and current spreading. Specify acceptance per IPC‑6012 Class 2 or Class 3 as required by your reliability target, and document hazardous‑substance control with RoHS/REACH.

Build and compliance options at HyperPCB

We build and inspect to IPC Class 2 or Class 3 acceptance criteria, support RoHS and REACH compliance, and operate an ISO 9001:2015 certified QMS (SGS certificate CN‑2023‑Q1156, valid until June 2027). Quotes are returned within 24 hours and DFM feedback within 1 business day.