Parallel MOSFETs not sharing current? Gate drive and PCB fixes that work

Parallel MOSFETs often fail to share because Vth, Rds(on), gate charge, and parasitic inductance vary; use per‑FET source and gate resistors, adequate gate‑driver current, symmetric Kelvin layout, and thermal coupling to restore balance.

Why do parallel MOSFETs hog current at the edges?

During turn‑on/off the device with the lowest effective gate impedance or lowest Vth reaches the Miller plateau first and takes more current. Small differences in gate charge (Qg), gate resistance, and loop inductance (package + PCB) cause unequal di/dt. At 100 A/µs, even 2 nH of unequal source inductance makes ~0.2 V error (V = L·di/dt), enough to shift current heavily. Once hot, positive Rds(on) tempco helps DC sharing, but switching transients dominate loss and stress.

What values should I start with for ballast and gate resistors?

Use a small source (ballast) resistor per MOSFET so its I·R drop swamps device mismatch:

• Target 20–50 mV drop at the intended per‑device current. Example: 30 A per FET → Rs ≈ 0.7–1.7 mΩ (30 mV/30 A to 50 mV/30 A). Power per resistor P ≈ I²·Rs → 0.9 W at 30 A and 1 mΩ; choose a low‑ohm shunt (e.g., 2512/3920) or copper bar sized for heat.

• Add an individual gate resistor per FET (start 4.7–10 Ω). Avoid a single shared gate resistor; it couples devices. If you also use a small series resistor at the driver pin (0–2.2 Ω), keep it much smaller than the per‑FET resistors.

How much gate‑driver current do you need?

Total gate charge adds. Estimate switching time from t ≈ Qg_total / I_driver. Example: four MOSFETs, each Qg = 80 nC → Qg_total = 320 nC. A 3 A driver gives ~107 ns to traverse the plateau; a 1 A driver would take ~320 ns, increasing losses and mismatch. Ensure the driver can both source and sink similar peak current to control dV/dt and prevent shoot‑through. Keep gate traces short and equal so the effective RG and LG seen by each FET match.

PCB layout that makes devices share

• Symmetric, star‑connected power paths: equal drain and source copper lengths/widths so each device sees the same DC and AC impedance. Aim for trace/strap length matching within a few mm; a straight PCB trace is roughly ~1 nH/cm, so ±5 mm mismatch adds ~±0.5 nH.

• Kelvin source to the driver: run a separate, low‑inductance return from each source (or the common source node) back to the gate‑driver ground. Do not share the high‑current source path for the driver return.

• Place the driver centered among the MOSFETs; keep each gate lead <20 mm and avoid vias; if vias are unavoidable, match count and placement per device.

• Decoupling at the switching loop: put several 0.1–1 µF X7R MLCCs as close as possible across the high‑current loop (drain bus to source/ground) to minimize ESL, backed by bulk capacitance. Add an RC snubber if ring‑down exceeds device ratings.

• Use a solid reference plane (4‑layer stackups are helpful) to cut loop inductance; avoid skinny neck‑downs near the devices.

Are you operating in the linear region or violating SOA?

Paralleling MOSFETs for linear (analog) operation is risky; Vth spread causes runaway unless you implement active sharing. In switching applications, still check SOA for turn‑on/off and avalanche. If you need linear control or very high currents, consider a power module or a single larger MOSFET before paralleling many small ones.

Thermal coupling and device selection

Mount devices on the same heat spreader so temperature rises track, reinforcing DC sharing. Use identical part numbers, preferably same lot. Verify heatsink interface uniformity; a 10 K difference can shift current materially because Rds(on) typically rises ~0.4–0.7%/K.

Bring‑up and debug checklist

• Measure each gate at the pin with a low‑inductance probe; confirm matched plateau timing.

• Add/trim per‑FET gate resistors until turn‑on/off overlap aligns within ~10–20 ns.

• Log per‑FET current using small Rs (1–2 mΩ) or a Rogowski/CT; aim for <10% mismatch at your operating di/dt.

• Check VDS overshoot; V = L·di/dt gives you a target for layout/decoupling improvements.

• Infrared or thermocouples: steady‑state ΔT between devices <5–10 K is a good sign.

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