PCB assembly: concrete SMT reflow, THT soldering, and test parameters

PCB assembly runs through stencil printing, placement, SAC305 lead‑free reflow with a 235–245 °C peak, post‑reflow inspection, THT soldering by wave (≈255–265 °C) or selective, cleaning as required, and electrical test.

What files and fiducials are required?

Provide Gerber or ODB++ data, BOM with MPNs and alternates, XY/CPL with a clear rotation convention, and assembly notes. Panel rails of 5–10 mm on two sides ease conveyor handling. Use three global fiducials per panel plus local fiducials for fine‑pitch parts; a common choice is 1.0 mm copper fiducial with ≈2.0 mm soldermask clearance. For in‑circuit test, reserve test pads ≥0.9–1.0 mm on a 50–100 mil grid with solid ground returns.

Stencil, paste, and printing parameters

Laser‑cut stainless stencils typically run 80–130 µm. For 0402 and 0.5 mm pitch QFP, 100–120 µm works well; step‑down regions are advisable for 0.4 mm pitch. Keep stencil area ratio >0.66 to avoid insufficient paste. Aperture reductions of 10–20% (e.g., home‑plate on gull‑wing, windowpane on QFN thermal pads) help control bridging and voids. No‑clean SAC305 paste per J‑STD‑005 Type 3 (≥0.5 mm pitch) or Type 4 (0.4 mm pitch) is common.

How is SAC305 reflow profiled?

• Ramp: 1.0–3.0 °C/s to soak

• Soak: 150–180 °C for 60–120 s

• Time above liquidus (217 °C): 40–90 s

• Peak: 235–245 °C, bounded by component ratings

• Cool: 3–4 °C/s

Double‑sided builds usually reflow the lighter side first to minimize part drop.

How are BGAs and QFNs inspected?

Post‑reflow AOI checks presence, polarity, skew, opens, and bridges. For hidden joints (BGA, LGA, QFN), 2D/3D X‑ray assesses ball collapse, bridging, head‑in‑pillow indicators, and voiding. Voiding targets depend on device notes; power QFNs often aim for ≤20–30% voiding on the thermal pad. QFN thermal pad apertures use a windowpane to control float and outgassing.

Through‑hole soldering options and settings

For mixed‑technology boards, wave solder typically preheats the topside to ≈100–130 °C, with a lead‑free pot around 255–265 °C and 2–4 s contact (chip wave then laminar wave). Use glue dots only when bottom‑side SMT must pass through wave. Selective solder applies flux, localized preheat, and nitrogen‑inerted nozzles; lead‑free pots commonly run ≈270–290 °C with 1–3 s dwell per pin, tuned to pin mass and hole fill. THR (reflow‑through‑hole) and press‑fit are options when mechanical strength or coplanarity dominates.

Cleaning and protective finishes

No‑clean flux residues are normally left in place unless test, coating, or reliability requirements dictate cleaning. Water‑soluble flux must be fully removed to prevent corrosion and leakage. When ionic cleanliness is specified, limits are typically referenced to IPC J‑STD‑001 (e.g., ROSE NaCl equivalence). Conformal coatings (acrylic, urethane, silicone) are commonly applied to ≈25–75 µm; mask connectors, test pads, and any keep‑out regions.

What controls apply to MSL and ESD?

For moisture‑sensitive devices, J‑STD‑033 defines floor life, storage, and bake recovery when exposure is exceeded (bake temperature and time depend on MSL and package). For electrostatic protection, ESD control programs are widely referenced to ANSI/ESD S20.20; packaging, grounding, and handling should align with device sensitivity levels.

Test access and acceptance criteria

ICT favors accessible, soldermask‑defined test pads at ≥0.9–1.0 mm with consistent grid spacing, plus low‑impedance returns to reduce false opens. Flying probe suits NPI and low volumes with minimal NRE. Functional test often includes firmware load, boundary scan, and power sequencing to rated loads. Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria per the drawing.

Which design choices raise SMT yield?

To curb tombstoning on 0402/0201, balance pad geometry and copper thermals, and reduce paste on the hotter pad by about 10–20%. For fine‑pitch bridging, improve gasketing, use home‑plate/dog‑bone apertures, and select paste type/viscosity matched to pitch. Minimize warpage by balancing copper across layers, adding 5–10 mm rails with three global fiducials, and considering stiffeners on thin builds.

Quality and compliance at HyperPCB

HyperPCB maintains an ISO 9001:2015 certified quality management system (SGS certificate CN-2023-Q1156, valid until June 2027). RoHS and REACH compliance is supported for hazardous substance control.