PCB impedance control: exact specs, tolerances, stackup, and testing

Impedance control requirements are the concrete items you hand the fabricator: per‑class targets (e.g., 50 Ω single‑ended; 90/100 Ω differential), the tolerance window (±10% unless you mandate ±8% or ±5%), full stackup with core/prepreg thickness and Dk at the test frequency, reference planes, finished copper, solder mask coverage, surface finish, and the verification method (IPC‑TM‑650 2.5.5.7 TDR on production coupons).

What must be on the fab drawing and PO?

• Target and tolerance per impedance class and structure: e.g., “L1 microstrip 50 Ω SE ±8%”, “L3 symmetric stripline 100 Ω diff ±10%”

• Layer numbers and reference planes for every controlled trace/pair

• Full stackup: core/prepreg type and thickness (e.g., 0.18 mm 7628; 0.10 mm 2116), resin content, and intended Dk at your test frequency

• Copper: starting and finished copper on all signal layers (e.g., 1 oz start, 35 µm finished)

• Solder mask: over‑mask or clearance on controlled microstrips (mask typically lowers Z by ~2–5%)

• Surface finish (OSP, ENIG, etc.) and any assumptions used in modeling

• Test: IPC‑TM‑650 2.5.5.7 TDR (or VNA fixture if you require S‑parameters), step rise time/time window, coupon style and dimensions

• Acceptance: tolerance, coupon location/quantity (e.g., one per panel per impedance class), and disposition for out‑of‑window results (waiver/rework/scrap)

• Net classes that require control, keepouts, and the length/regions where control applies

Typical targets and solvable starting geometries

For FR‑4‑class laminates with Dk ≈ 3.7–4.1 at ~1 GHz (always solve with your laminate data):

Outer‑layer microstrip, h ≈ 0.18 mm to plane (one ply 7628), 35 µm copper: 50 Ω single‑ended near w ≈ 0.32 mm. 100 Ω differential with w ≈ 0.32 mm and s ≈ 0.30–0.35 mm. 90 Ω differential with the same w and s ≈ 0.20–0.25 mm. Solder mask (Er ~3.2–3.6) typically reduces Z by ~2–5%.

Inner‑layer symmetric stripline, dielectric to planes ≈ 0.20 mm, 35 µm copper: 50 Ω single‑ended at w ≈ 0.30–0.34 mm. 100 Ω differential near w ≈ 0.18–0.22 mm with s ≈ 0.20–0.30 mm. Reducing dielectric to ≈0.10–0.12 mm pushes 50 Ω stripline widths toward ~0.16–0.22 mm. Use a 2D field solver (IPC‑2141A design guidance) with your Dk/Df, copper roughness, and etch profile.

What tolerance is realistic and how is it accepted?

If you do not state a window, many fabs apply ±10% lot acceptance. Tighter windows (±8% or ±5%) are feasible with controlled laminate and coupon tuning; specify which classes/nets require the tighter window. Verification commonly uses IPC‑TM‑650 2.5.5.7 TDR on representative coupons matching geometry and stackup. For stable results, coupon length ≥100 mm and 35–50 ps step rise times are typical; acceptance uses the flat, steady‑state section, excluding launches/fixtures. State if on‑board probing is required and provide landings. For differential, call out odd‑mode measurement and fixture to avoid mode conversion. Lot acceptance for rigid boards follows IPC‑6012.

What drives impedance variation in production?

Dielectric thickness: press variance of ±10–15 µm on thin buildups can shift Z by several ohms; specify targets and allowed ranges per dielectric. Copper thickness: outer‑layer plating adds ~10–20 µm, lowering Z; call out finished copper for signal layers. Etch profile: sidewall taper and over/under‑etch change effective width; specify whether widths are at copper base and let the fab apply etch compensation. Solder mask: covering microstrips lowers Z; define mask clearances if you modeled air. Material Dk: weave/resin content move Z and can skew differential timing; tighter weaves (e.g., 2116/3313 vs 7628) reduce spread. Copper roughness affects loss more than Z0, but extreme roughness slightly lowers effective impedance.

Microstrip or stripline for high‑speed links?

Pick microstrip when you need easy tuning and access on outer layers, short routes, and can manage EMI with returns and stitching. Expect higher radiation and larger weave‑induced skew than stripline; for long 10+ Gbps pairs, that skew can reach several ps/in on coarse weaves. Choose symmetric stripline when shielding is required, you can keep continuous planes above/below, and you want tighter coupling and lower skew; thin dielectrics (≈0.10–0.12 mm) help maintain 100 Ω differential with narrower lines and reduce pair‑to‑pair variation. Avoid any plane splits or voids under controlled lines in either case.

RF and low‑loss notes

Above a few GHz, dispersion (frequency‑dependent Dk/Df), glass weave, and roughness dominate behavior. Provide frequency‑specific Dk/Df from the laminate data sheet and model with the vendor’s effective Dk. If you require frequency‑domain acceptance, add S‑parameter masks (magnitude of S11/S21 and Z0 vs. frequency) along with the time‑domain TDR target. Mask over microstrip lowers Z and slightly increases effective dielectric loading; include mask thickness/Er in your model.

Quality, standards, and compliance options

Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria. RoHS and REACH compliance is supported for hazardous substances. Our quality management system is ISO 9001:2015 certified (certificate no. CN‑2023‑Q1156, issued by SGS, valid until June 2027). For RF programs, our partner factory manufactures its own high‑frequency laminates and supplies RF PCB fabricators in China, including publicly listed PCB companies.