PCB prototype assembly: which files and DFM rules matter most?

You need complete fab and assembly data—Gerbers/ODB++, a BOM with exact MPNs, and a centroid file—plus DFM such as 0.10 mm trace/space, 0.30 mm finished vias with 0.15 mm annular ring, ≥0.25 mm copper‑to‑edge, 0.05–0.10 mm solder‑mask expansion, and a stencil matched to your smallest pitch.

What files does PCB prototype assembly require?

• Gerber RS‑274X or ODB++ (layers, mask, paste, drill, board outline, readme)

• BOM (CSV/XLSX): refdes, manufacturer + MPN, value, tolerance, voltage/temp ratings, package, DNP/DNI flags, approved alternates

• Centroid/pick‑and‑place (CSV/TXT): refdes, X/Y in mm, rotation, side, package, MPN

• Assembly drawing (PDF): polarity, pin‑1, fiducials, keepouts, height limits, notes

• Schematic (PDF) for reference and test points

• Netlist (IPC‑D‑356) for electrical checks (optional but helpful)

• Panel drawing if you pre‑panelize; otherwise allow rails to be added

• Test/firmware notes for bring‑up and programming headers

DFM rules that prevent respins

For mainstream FR‑4 prototypes (Tg ≥ 150 °C), 1 oz (35 µm) copper on outers and 0.5–1.0 oz on inners is common. As starting constraints: 0.10 mm/0.10 mm (4/4 mil) trace/space, 0.30 mm finished vias with 0.15 mm annular ring, hole‑to‑copper ≥ 0.25 mm, copper‑to‑edge ≥ 0.25 mm, silkscreen line width ≥ 0.15 mm. Keep solder mask dam ≥ 0.10 mm between pads to avoid mask “slivers.” For thermals, balance copper around 0402/0201 pads to reduce tombstoning. Follow IPC‑7351 for land pattern geometry and IPC‑6012 for bare board criteria.

Example 4‑layer stackups and impedance targets

A common 4‑layer stack is L1 signal (35 µm), L2 ground (35 µm), L3 power (17–35 µm), L4 signal (35 µm). With L1‑L2 dielectric ≈ 0.18–0.20 mm (e.g., 2116/1080 or 7628 prepreg, εr ≈ 3.6–3.8): outer microstrip 90 Ω differential often lands near 0.15–0.20 mm trace width with 0.15–0.20 mm spacing; inner stripline 100 Ω differential may be 0.10–0.13 mm width with 0.15–0.20 mm spacing when L2‑L3 dielectric ≈ 0.20 mm. Always request a field‑solver check; impedance depends on exact resin content and copper roughness. Typical targets: USB 2.0 and USB 3.x 90 Ω diff, Ethernet 100 Ω diff, PCIe 85 Ω diff, MIPI 90 Ω diff.

What stencil thickness should you pick?

For mixed technology: 0.12–0.13 mm (4.7–5.1 mil) suits 0402–0.5 mm QFP well. For 0.4 mm‑pitch BGAs or many 0201 parts, consider 0.10 mm (4 mil). Use Type 4 or Type 5 paste for fine pitch. Reduce QFP apertures ~10% area to limit bridging; windowpane thermal pads to ~50–70% paste coverage. Maintain stencil fiducials and a smooth aperture transition where density changes.

How to handle BGAs and 0.4 mm pitch?

For 0.5 mm pitch, NSMD pads around 0.25–0.28 mm work well; for 0.4 mm, 0.20–0.23 mm pads are typical. Dog‑bone fanout with 0.10 mm traces and 0.20–0.25 mm microvias to a solid plane is common; via‑in‑pad should be filled and plated if used. Keep mask openings tight to preserve dams; consider solder‑mask defined pads only when copper pads are too close for NSMD. Plan for X‑ray inspection on early prototypes.

Panelization and fiducials

Add 8–10 mm rails on two opposite sides for handling. Use three global fiducials (1.0 mm copper with 3.0 mm clearance) on the panel and local fiducials near fine‑pitch parts. Provide 2–3 mm tooling holes in rails. V‑score with 0.40–0.50 mm web or mouse‑bites with 0.50 mm holes on ~1.0 mm pitch; keep components ≥ 1.0 mm from score lines or break tabs.

Reflow profile and paste considerations

For SAC305 lead‑free paste: preheat 150–200 °C, 60–120 s soak, ramp 1–3 °C/s, 30–90 s above 217 °C, peak 235–245 °C, cooldown ≤ 4 °C/s. For Sn63/Pb37: peak ~205–215 °C. Observe MSL handling; parts rated MSL3+ may need baking (e.g., 125 °C for 24 h) if bags are open too long.

Test and bring‑up on day one

Expose test pads (≥ 0.5 mm) for power rails, clocks, reset, and key IO. Add a 100 mil SWD/JTAG or Tag‑Connect footprint. Use a current‑limited bench supply on first power‑up; verify resistance to ground on each rail, then ramp and check inrush. Boundary‑scan can validate BGA connectivity when ICT is unavailable. For workmanship, IPC‑A‑610 Class 2 acceptance is the usual target for prototypes.

How fast can you get a quote and review?

HyperPCB returns quotes within 24 hours and DFM feedback within 1 business day. HyperPCB’s quality management system is ISO 9001:2015 certified (certificate CN‑2023‑Q1156 by SGS, valid until June 2027).

Parts risk and alternates

In the BOM, list second‑source MPNs for regulators, logic, passives (same package, tolerance, voltage, ESR, height). Call out no‑substitute parts explicitly. Note any parts to DNI for variant builds and keep tall components away from V‑score lines to protect them during depanelization.