PCB prototype machine vs outsourcing: hard specs, IPC limits, break-even

Direct answer: use a benchtop PCB machine for same‑day 1–2 layers with ≥6/6 mil trace/space, unplated vias or eyelets/rivets, drilled holes ≥0.30–0.35 mm, loose impedance (±15–20%), and simple bring‑up. Outsource when you need plated through holes to IPC‑6012 (≥20 μm Class 2; ≥25 μm Class 3), ≤0.5 mm‑pitch BGAs, controlled impedance (single‑digit percent), solder mask/surface finishes, or multilayers.

What can a benchtop machine actually build?

Isolation‑milling or UV‑laser‑patterned resist + etch both work well for fixtures, breakout boards, and analog/power prototypes where 35 μm copper and 6/6 mil geometry suffice. Expect double‑sided registration error around ±50–100 μm without vision alignment. Z‑axis control and spindle runout matter; ≲10 μm runout helps keep isolation cuts consistent so pads don’t undercut.

PTH copper and impedance control limits

Desktop through‑hole plating is the hardest step to make reliable across panels. IPC‑6012 requires minimum hole‑wall copper thickness of about 20 μm (Class 2) and 25 μm (Class 3); hobby/desktop lines often deposit thinner, nonuniform copper and cannot replicate factory interconnect stress testing. Impedance control also suffers because laminate thickness and Dk vary more at bench scale. As a reference point (per IPC‑2141 style microstrip equations): on FR‑4 (Er≈4.2) with 35 μm copper over a 0.18–0.20 mm dielectric (e.g., a 7628‑style ply), a 50 Ω microstrip tends to be ~6–8 mil wide; a 90 Ω differential pair may be two ~5–6 mil traces with ~6–8 mil gap. Without well‑controlled dielectric, plan for ±15–20% impedance variation; professional fabs typically hold single‑digit percent with controlled stackups and coupons.

Benchtop realistic limits you can plan on

• Layers: 1–2 layers are routine. Four layers need lamination/registration tooling; beyond that is uncommon on a bench.

• Trace/space: 6/6 mil is repeatable with sharp tools; 4/4 mil is possible on flat copper but yield is tool‑ and setup‑sensitive.

• Drilling: 0.30–0.50 mm mechanical drills for acceptable hole quality; microvias and blind/buried vias are out of scope.

• Registration: ±50–100 μm typical for two‑sided alignment without vision fiducials.

• Solder mask/silkscreen: often omitted or done with dry‑film/inkjet; expect limited registration and durability.

• Impedance: plan using measured dielectric thickness, but expect ±15–20% unless you control lamination.

• Materials: FR‑4 and polyimide are workable; PTFE‑based RF laminates are difficult to drill/laminate consistently on a bench.

• CAM/EHS: Gerber/Excellon support and height‑map probing help; manage dust/fumes and tool life explicitly.

Cost model and a concrete break‑even example

Define costs per spin: C = labor_rate × hours + consumables + amortization.

Example: labor_rate = US$100/h; hours = 2.0; consumables = US$15; machine = US$25k amortized over 3 years and 400 spins → amortization ≈ US$21/spin. Then C ≈ 100×2 + 15 + 21 = US$236 per 2‑layer spin. If a 24–48 h quick‑turn 2‑layer order costs US$180–300 for a small lot, internal work beats outsourcing only when your labor hours drop (e.g., 1.5 h → ~US$186) or when courier time, not cost, is the bottleneck. Multilayers, PTH, solder mask, and finishes rapidly flip the math in favor of outsourcing because bench capability gaps add time, scrap, or re‑runs.

RF and HDI: realistic or not?

For RF, dielectric thickness/Dk control and copper roughness dominate loss and impedance. Materials such as Rogers 4003C (Dk≈3.55±0.05) and smooth copper matter more than geometry tweaks; desktop processes rarely hold dielectric/copper parameters tightly enough for 2.4/5 GHz filters or 10+ Gbps channels. For HDI (microvias, stacked/buried vias), you need controlled lamination cycles, laser drilling, and copper filling—bench gear does not cover these.

Outsourcing capabilities at HyperPCB

• ISO 9001:2015 QMS certified (certificate CN-2023-Q1156 by SGS, valid to June 2027) [1]

• Quotes within 24 hours and DFM feedback within 1 business day [2]

• Build/inspection to IPC Class 2 or Class 3 acceptance criteria [5]

• RoHS and REACH compliance support [6]

• Partner factory AEGIS maintains ISO 9001:2015, ISO 14001:2015, ISO 45001:2018 management systems [3]

• Partner factory AEGIS also maintains ISO 13485:2016 and IATF 16949 [4]

• Partner factory manufactures its own high‑frequency laminates and supplies RF PCB fabricators in China, including publicly listed companies [7]

Decision gates you can apply today

• In‑house: 1–2L, ≥6/6 mil, holes ≥0.30–0.35 mm, unplated vias acceptable, impedance ±15–20%.

• Outsource: IPC‑6012 PTH, ≤0.5 mm‑pitch BGA, controlled impedance, multilayer, solder mask/finishes.