PCB Quote Comparison: normalize specs, cost drivers, and risk

To compare PCB quotes fairly, normalize the manufacturing spec and DFM assumptions before you compare unit price.

Normalize the build spec before price

Lock the exact build recipe so suppliers price the same thing: layer count and stackup (dielectrics and foil weights), finished thickness (e.g., 1.6 mm ±10%), copper (outer 1 oz, inner 0.5 oz unless specified), controlled impedance targets (50 Ω single‑ended, 90 Ω differential) with tolerance (±10% typical) and coupon requirement, minimum trace/space (e.g., 4/4 mil or 100/100 µm), minimum finished hole (e.g., 0.20 mm), max mechanical drill aspect ratio (≈10:1 typical), via types (through only vs blind/buried, microvia 0.10 mm), any via‑in‑pad and fill requirements, annular ring (e.g., ≥4 mil), solder mask type (LPI), dam width (e.g., ≥4 mil), surface finish (ENIG, HASL‑LF, immersion silver, OSP), legend color, panelization method (vendor or customer), electrical test (flying‑probe vs fixture), acceptance class (IPC Class 2 or Class 3), and compliance needs (RoHS/REACH). Quote the same documentation set (Gerber/ODB++, stackup table, fab notes, netlist) for each vendor.

Why do PCB quotes differ for the same files?

Vendors fill in missing inputs with their defaults. One may assume 0.5 oz inner copper, another 1 oz; one may route as through‑hole only, another may add microvias; one may quote ENIG, another HASL; one may panelize 18×24 in, another 20×24 in. These choices change drill counts, plating time, yield, and test/NRE, skewing price. Remove ambiguity up front.

What must be in your RFQ package?

Include Gerbers or ODB++, readme/fab notes, stackup with dielectric thicknesses (e.g., FR‑4 core/prepreg like 7628/2116), impedance table and coupon call‑outs, complete drill table with tolerances and backdrill (if any), controlled depth routing (if any), surface finish, solder mask/legend colors, acceptance class (IPC Class 2 or 3), electrical test method, panelization rules or finished panel drawing, RoHS/REACH requirement, and required certificates. Add a target panel utilization if you want consistent panel yield across quotes.

Quantify the big cost drivers

The largest levers are feature size, holes, finish, and panel yield. Tightening line/space from 4/4 mil to 3/3 mil often forces finer laminates and tighter registration, reducing yield. Dropping minimum finished via from 0.25 mm to 0.20 mm increases drill time and may push aspect ratio. Blind/buried and via‑in‑pad add lamination/laser/fill steps. ENIG costs more than HASL‑LF but improves planarity for 0.4 mm BGAs. Panel yield dominates: for a 100×100 mm board on an 18×24 in panel with ~12 mm margins, usable area ~420×510 mm fits roughly 20 pieces; if a different vendor assumes a 400×500 mm usable area, you may only get 16–18 per panel—normalize this before you compare.

How to compare quality and risk?

Ask for the acceptance class (IPC Class 2 or 3) and sample inspection plan, impedance test method/tolerance, AOI coverage, microsection frequency, solderability test (if any), and whether they offer DFM feedback before build. For HDI or RF, require the exact laminate family and Dk/Df targets; a PTFE or low‑loss hydrocarbon/ceramic stack with known Dk (e.g., 3.0–3.5) and tight Tg/CTE control prevents surprises in insertion loss and registration. Verify RoHS/REACH declarations align with your BOM and finish.

PCB quote comparison checklist

• Stackup with dielectric thicknesses, copper weights, and finished thickness

• Controlled impedance values, tolerance, and coupon requirement

• Min trace/space, min finished hole, annular ring, and aspect ratio

• Via plan (through, blind/buried, microvia), any via‑in‑pad and fill/cap

• Surface finish and solder mask/legend specs

• Panelization method and assumed usable panel area/yield

• Electrical test type (flying‑probe vs fixture) and NRE/fixture costs

• IPC acceptance class (2 or 3) and required reports/certs

• RoHS/REACH requirement and any special compliance docs

• Lead documentation: Gerber/ODB++, fab notes, stackup table, netlist

How HyperPCB supports apples‑to‑apples

We return quotes within 24 hours and DFM feedback within 1 business day, enabling you to lock a single normalized spec across vendors quickly. Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria, and RoHS and REACH compliance is supported. Our ISO 9001:2015 certified quality management system (certificate CN‑2023‑Q1156, SGS, valid until June 2027) governs quoting and manufacturing controls. Our partner factory AEGIS maintains ISO 9001:2015, ISO 14001:2015, and ISO 45001:2018 management systems, plus ISO 13485:2016 and IATF 16949 for regulated sectors. For RF work, our partner factory manufactures its own high‑frequency laminates and supplies RF PCB fabricators in China, including publicly listed PCB companies—useful when your comparison involves low‑loss material options and impedance coupons.

Should I use flying‑probe or fixture test?

Below a few hundred units or for frequent ECOs, flying‑probe avoids fixture NRE and is flexible. At higher volumes or when test time drives takt, fixture test amortizes its NRE over the lot and reduces unit cost. Compare quotes both ways if your volume may shift.

A quick sanity check before you decide

If one quote is >20% lower, verify that copper weights, finish, hole count, panel yield, impedance tolerance, and IPC class match your baseline. The cheapest quote is often assuming looser class, different finish, or fewer lamination/test steps—make them explicit and re‑quote.