PCB quote tool: required inputs and how pricing is computed

A practical PCB quote tool converts your design files and specs into cost from measurable drivers: board area/panel use, layer count, copper weight, drill complexity, tolerances, materials, and special processes.

What a PCB quote tool really calculates

Most engines price per panel, then divide by usable pieces. Key cost variables include: working panel utilization, layer stack complexity (e.g., sequential lamination for HDI), minimum trace/space (4/4 mil vs 3/3 mil), smallest finished hole and tool count, copper weight (1 oz = 35 µm; 2 oz = 70 µm), surface finish (HASL vs ENIG/ENEPIG), impedance-control requirements (test coupons, stack-up), and any special steps (via-in-pad, backdrill, edge plating).

Which files and specs should I upload?

• Fabrication data: Gerber X2 or ODB++, or IPC‑2581; include Excellon drills with plated/unplated noted

• Fab notes: layer count; outer/inner copper (e.g., 1 oz/0.5 oz); materials (e.g., FR‑4 Tg 170, glass styles 7628/2116/1080); stack‑up proposal; finish (HASL lead-free, ENIG, ENEPIG, OSP)

• Design rules: min trace/space (e.g., 4/4 mil), smallest finished hole (e.g., 0.25 mm), min annular ring (≥4 mil), soldermask dam (≥4 mil), hole-to-copper clearance (≥8 mil)

• Impedance targets: 50 Ω single‑ended; 90–100 Ω differential; tolerance (±10% typical, ±5% if required)

• Outline and mechanics: overall size, slots/cutouts, controlled depth if any, thickness (e.g., 1.6 mm), copper-to-edge clearance (≥10–20 mil)

• Quantities, array/panel requirements, X‑out policy, IPC acceptance class (2 or 3), RoHS/REACH declarations if needed

Which tolerances move the price the most?

Tighter line/space below 4/4 mil usually forces finer imaging and adds cost; ≤3/3 mil often shifts the build into HDI rules. Finished holes below 0.25 mm, or aspect ratio above ~8–10:1 (board thickness to drill diameter), reduce yield and add extra steps. Annular ring below 4 mil increases registration risk. Soldermask dams under 4 mil often need LDI and tighter control. Impedance tighter than ±10% can drive specific dielectrics and coupon testing. Heavy copper (>1 oz outer, >0.5 oz inner) increases etch time and can require larger spacing, affecting routing density and panelization.

Impedance control: stack-up, targets, and cost

Use realistic dielectrics and copper roughness when you enter impedance data. Examples engineers often use: on FR‑4 with εr ≈ 3.7–4.2 and 35 µm outer copper, a 50 Ω microstrip over ~0.17–0.20 mm dielectric tends to be ≈0.28–0.32 mm (11–13 mil) wide; a 100 Ω differential microstrip often uses gap ≈ width. For stripline between planes with ~0.20 mm dielectric and 18 µm copper, 50 Ω widths are commonly ~6–8 mil. State the target and tolerance (±10% is standard) and allow the fabricator to freeze the stack‑up and coupon. Listing specific prepregs (e.g., 2116 ≈0.10 mm, 1080 ≈0.075 mm, 7628 ≈0.18 mm after lamination) helps tools predict impedances.

How panelization changes your unit price

Unit cost ≈ panel_price ÷ usable_pieces. Usable_pieces = floor((W−2·rail)/(bw+spacing)) × floor((H−2·rail)/(bh+spacing)). Typical rails: 10 mm; rout web/clearance: 2–3 mm. Adding break‑offs or rotation can improve fit. If you need V‑cut, add web constraints; if you require zero X‑outs, yield assumptions rise and unit price follows.

How fast do I get a quote and DFM feedback?

Quotes are returned within 24 hours and DFM feedback within 1 business day. [Ref: internal process]

Compliance and acceptance options

Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria. RoHS and REACH compliance is supported for hazardous substance control. Our quality management system is ISO 9001:2015 certified (SGS CN‑2023‑Q1156, valid to June 2027). For programs requiring medical or automotive QMS, our partner factory AEGIS maintains ISO 13485:2016 and IATF 16949, in addition to ISO 9001:2015, ISO 14001:2015, and ISO 45001:2018.

Common pitfalls that delay quotes

Conflicting stack‑up notes vs copper weights; missing drill plating state; unspecified controlled impedance tolerance; outline without slot dimensions or radius; BOM or finish mismatches (e.g., ENIG called on drawing but HAL in fab notes); panel vs single‑piece deliverables not stated; IPC class absent while annular ring/clearance imply Class 3.