PCB stackup calculator guide with formulas, FR‑4 examples, and 4/6/8‑layer stacks

What does a stackup calculator output?

It numerically predicts characteristic and differential impedance, delay, and coupling for microstrip and stripline. On FR‑4, microstrip delay is commonly 140–170 ps/in; stripline is about 160–190 ps/in. As a concrete example, for FR‑4 with Dk ≈ 3.8 at ~1 GHz, 35 µm copper, and a single 7628 ply to the plane (h ≈ 0.18 mm), a 50 Ω microstrip solves to roughly 0.32 mm width. If h is 0.10 mm (one 2116 ply), the 50 Ω width is near 0.16 mm. Outer‑layer solder mask around 20–30 µm (Dk ≈ 3.2) usually lowers microstrip impedance by ~2–5%.

A concrete 50 Ω microstrip sizing on FR‑4

Using the IPC‑2141/Hammerstad microstrip model, Z0 ≈ (87/√(εr+1.41))·ln(5.98·h/(0.8·w+t)). For εr = 3.8, h = 0.18 mm, t = 0.035 mm, solving gives w ≈ 0.32 mm for 50 Ω. Swapping h to 0.10 mm (2116 prepreg) yields w ≈ 0.16 mm. Keeping h = 0.18 mm but adding solder mask typically drops Z0 by ~3%, so you might narrow w a few percent to recover 50 Ω. Always plug your laminate’s frequency‑specific Dk/Df into a field solver for the final number.

4‑, 6‑, and 8‑layer FR‑4 stack examples

4‑layer, nominal 1.6 mm: place L1 signals over a solid L2 ground. With L1–L2 spacing of one 7628 ply (~0.18 mm) and 35 µm copper, 50 Ω microstrips tend to land near 0.30–0.34 mm. If you instead use ~0.10 mm to the plane (one 2116), widths fall near 0.15–0.20 mm. For 6‑layer, a common high‑speed topology is L1 SIG, L2 GND, L3 SIG (stripline to L2/L4), L4 PWR, L5 GND, L6 SIG. With ~0.18 mm from L3 to each plane and FR‑4 Dk ≈ 3.8, 50 Ω striplines are often about 0.20–0.28 mm. On dense 8‑layer builds, keep each signal layer adjacent to a solid plane to contain fields and manage crosstalk; balance cores and prepregs by glass style (e.g., 7628 ≈ 0.18 mm, 2116 ≈ 0.10 mm, 1080 ≈ 0.07 mm) to control warp.

Differential pairs: what gaps for 90 Ω and 100 Ω?

The following are workable starting points on FR‑4 with 35 µm copper:

• 100 Ω microstrip, h ≈ 0.18 mm: w ≈ 0.30–0.32 mm, s ≈ 0.30–0.45 mm (≈1.0–1.5×w)

• 90 Ω microstrip (USB 2.0 HS), h ≈ 0.18 mm: w ≈ 0.30–0.32 mm, s ≈ 0.20–0.30 mm (≈0.7–1.0×w)

• 85 Ω stripline (PCIe/USB 3.x): with ~0.15–0.20 mm to each plane, w ≈ 0.20–0.25 mm, s ≈ 0.20–0.30 mm

Validate with a 2D field solver using the laminate’s Dk at your signaling frequency and include solder mask for outer layers.

How close are calculations to fabricated results?

Impedance moves with geometric and material tolerances. Quantitatively, take the 50 Ω microstrip above (h = 0.18 mm, w = 0.32 mm, t = 0.035 mm, εr = 3.8):

• Dielectric height h ±10% (0.162–0.198 mm) shifts Z0 to roughly 45.8–53.5 Ω (about −4.2 to +3.5 Ω).

• εr ±0.2 moves Z0 by about −0.9 to +1.1 Ω.

• Copper thickness t ±10 µm changes Z0 by about −1.2 to +1.4 Ω.

• Width w ±25 µm can swing Z0 by about −2.5 to +2.8 Ω.

• A 25 µm solder mask over microstrip commonly lowers Z0 by ~2–5% (e.g., 50 Ω to ~47.5–49 Ω).

These numbers explain why coupon tolerances of ±10% are typical. Lock exact ply styles and counts, use Dk/Df at your operating frequency, and correlate measured coupon results back into your calculator library.

Tools and data to use with confidence

For first‑pass sizing, IPC‑2141 equations work. For sign‑off, use a field solver: Saturn PCB Toolkit (free) for quick checks, commercial solvers such as Polar Si9000, or EDA‑integrated solvers. Always use laminate vendor datasheets at the relevant frequency; FR‑4 families often show Dk ~3.6–4.2 (≈1 GHz) with Df ~0.012–0.02, while low‑loss materials can be Dk ~3.0–3.4 with Df ~0.0015–0.005.

Manufacturing and compliance facts

Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria. RoHS and REACH compliance is supported. Our quality management system is ISO 9001:2015 certified (certificate CN‑2023‑Q1156, SGS, valid to June 2027). Our partner factory manufactures its own high‑frequency laminates and supplies RF PCB fabricators in China, including publicly listed PCB companies.