PCB stackup design guide with rules, numbers, and a printable checklist

Below are concrete stackup rules, numeric examples, and a printable checklist you can save as a PDF.

What does the stackup control?

It sets impedance, loss, crosstalk, EMI, PDN inductance, warpage risk, and cost by fixing dielectric thicknesses, copper weights, plane references, and laminate Dk/Df before routing.

How many layers do I need for impedance and EMI?

Use 4 layers when one high‑speed routing side can reference a continuous L2 ground and slower signals live on L4; keep L1–L2 dielectric ~0.18–0.20 mm so 50 Ω and 100 Ω are practical with 1 oz copper. Move to 6 layers when you need two orthogonal high‑speed layers with tight crosstalk control (e.g., <3–5% near‑end) and uninterrupted planes adjacent to every signal; interleave planes so no signal layer is more than one dielectric from a solid plane. Go 8 layers when you have multiple multi‑Gbps buses (e.g., >8 differential pairs) that must be shielded by planes and you also need a thin PDN cavity (≈0.08–0.12 mm) for low spreading inductance.

Materials, Dk/Df, and thickness references

FR‑4 Dk ≈3.7–4.3 at 1 GHz; Df ≈0.012–0.02. Low‑loss laminates: Dk ≈3.3–3.7; Df ≈0.002–0.006. Copper thickness: 0.5 oz ≈ 17 µm; 1 oz ≈ 35 µm; 2 oz ≈ 70 µm. Typical pressed prepregs per ply: 106 ≈ 0.04–0.06 mm; 1080 ≈ 0.07–0.08 mm; 2116 ≈ 0.11–0.13 mm; 7628 ≈ 0.17–0.20 mm. Common cores: 0.10, 0.18, 0.20, 0.36 mm. Confirm with IPC‑4101 datasheets and the fabricator’s laminate set.

Which glass styles reduce fiber‑weave skew?

Prefer spread or balanced glass (e.g., 2116, 3313). For very tight timing, avoid depending on coarse 7628 beneath long differential pairs. Bias routes 10–15° relative to weave to average the resin fraction seen by each line in a pair.

What impedances should I specify and how tight?

Single‑ended: 50 Ω microstrip/stripline is standard. Differential: USB 2.0 90 Ω; USB 3.x and PCIe 85 Ω; HDMI/DisplayPort/SATA/LVDS/Ethernet 100 Ω. Tolerance is typically ±10% unless the interface budget demands tighter. Specify TDR coupon measurement (IPC‑TM‑650 2.5.5.7) with acceptance to IPC‑6012 Class 2 or Class 3 as applicable.

Width/spacing starting points you can verify

Use a field solver and your exact laminate data; the values below are reproducible starting points for Er ≈ 4.1.

4‑layer microstrip (L1 over L2 GND), dielectric ≈0.18 mm, 1 oz: 50 Ω width ≈ 0.30–0.38 mm; 100 Ω differential: w ≈ 0.25–0.30 mm, s ≈ 0.25–0.30 mm. 6‑layer symmetric stripline in 0.20 mm core (0.10 mm to each plane), 0.5 oz: 50 Ω width ≈ 0.12–0.16 mm; 100 Ω differential: w ≈ 0.10–0.12 mm, s ≈ 0.12–0.16 mm; 90 Ω differential (USB 3.x) with same core: w ≈ 0.10–0.12 mm, s ≈ 0.14–0.18 mm. PCIe 85 Ω differential in that stripline stack often lands at w ≈ 0.10–0.12 mm, s ≈ 0.10–0.14 mm. Copper roughness and resin content shift these; co‑design the coupon.

Reference planes and return current control

Place a solid plane adjacent to every signal layer. Do not route across plane splits; when a split crossing is unavoidable, add stitching via pairs within ~1 mm of both edges of the split to provide a low‑inductance return path. To reduce radiation, keep fast lanes as stripline; keep microstrip runs short near I/O.

PDN cavities and decoupling geometry

Tighten plane‑to‑plane spacing to ~0.08–0.12 mm for low spreading inductance in high di/dt regions. Keep the cap‑via to IC‑via loop short: place the decoupling capacitor so that pad‑to‑via‑to‑plane distance keeps total loop length within a few millimeters; via farms near high di/dt loads help.

Current and heating per IPC‑2152

Size power traces and copper pours with IPC‑2152, considering copper thickness, allowable temperature rise, and airflow. Parallel planes or large pours reduce resistance and improve heat spreading; document the allowed temperature rise for each high‑current net.

Example 4‑, 6‑, and 8‑layer stacks you can build

4‑layer: L1 Signal, L2 GND (solid), L3 PWR (solid), L4 Signal. Use L1–L2 ≈ 0.18–0.20 mm (e.g., 1080+2116); core ≈0.20 mm; L3–L4 ≈ 0.18–0.20 mm. Route controlled‑impedance on L1; keep L2 uninterrupted.

6‑layer: L1 Sig, L2 GND, L3 Sig (stripline), L4 Sig (stripline), L5 PWR, L6 GND. Keep L3/L4 ~0.10–0.12 mm from adjacent planes for crosstalk and impedance control; keep L2 and L5 continuous.

8‑layer: L1 Sig, L2 GND, L3 Sig, L4 GND, L5 PWR, L6 Sig, L7 GND, L8 Sig. Bury critical differential pairs on L3/L6; L2/L4 and L7/L5 serve as shields and PDN cavities.

Release‑to‑fab data you must include

Call out dielectric thicknesses and material grades (not just prepreg codes), target impedances with tolerance and coupon type, any glass style constraints, copper weights by layer with finished thickness tolerance, and acceptance to IPC‑6012 Class 2 or Class 3. If hazardous‑substance control is required, state RoHS/REACH. Archive solver inputs/outputs and reference the version used.

Printable stackup checklist

• Target impedances (SE/Diff), tolerances, and coupon (IPC‑TM‑650 2.5.5.7)

• Material family/grade, Dk/Df vs frequency, glass style constraints

• Copper weights per layer and finished thickness tolerances

• Dielectric thicknesses by interface (e.g., L1–L2 = 0.18 mm)

• Plane assignment, split rules, and stitching‑via strategy

• PDN cavity thickness targets and decoupling placement rules

• Impedance model source, version, and archived solver outputs

• Acceptance per IPC‑6012 Class 2/3; test report requirements

• RoHS/REACH status; UL/flame‑class and warpage limits if needed

• Panelization notes (rail width, thieving, coupons, arrays)

Compliance and services you can rely on

Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria. RoHS and REACH compliance is supported for hazardous substance control. Our quality management system is ISO 9001:2015 certified (certificate CN‑2023‑Q1156, issued by SGS, valid until June 2027). Quotes are typically returned within 24 hours, and DFM feedback within 1 business day.