PCB stackup explained: impedance, materials, and practical examples

A PCB stackup is the ordered arrangement of copper and dielectric layers that sets impedance, EMI/EMC behavior, power integrity, thickness, and cost.

What is a PCB stackup?

A stackup combines copper foils, dielectric cores, and prepregs pressed into a laminate. Key variables are layer count, copper weight (typically 0.5 oz ≈ 17 μm, 1 oz ≈ 35 μm), dielectric thickness after lamination, resin/glass style (e.g., 106, 1080, 2116, 7628), and resin system (standard FR‑4 vs low‑loss).

Why stackup drives impedance and EMI

Impedance depends on trace geometry and its distance to a solid reference plane. Microstrip (outer layer over a plane) and stripline (inner layer between two planes) dominate high‑speed design. Tight plane coupling lowers loop area and radiated emissions. Poor plane adjacency forces return currents through gaps, raising crosstalk and EMI.

Typical materials and thicknesses

• FR‑4 effective Dk ≈ 3.7–4.0 at 1 GHz; loss tangent ≈ 0.015–0.02.

• Low‑loss resin systems can offer Dk ≈ 3.2–3.5 and loss tangent ≈ 0.002–0.006 for multi‑Gbps links.

• Common pressed prepreg thickness per ply: 106 ≈ 0.05 mm, 1080 ≈ 0.076 mm, 2116 ≈ 0.11–0.12 mm, 7628 ≈ 0.17–0.18 mm.

• Core thicknesses: 0.1, 0.2, 0.5, 0.8 mm are common building blocks.

Note: outer layers gain 8–15 μm plating during fabrication; include it in impedance models.

What impedances are most common?

• Single‑ended 50 Ω for many RF and high‑speed traces

• Differential 90 Ω for USB 2.0 D+/D−

• Differential 85 Ω for PCIe and many SerDes

• Differential 100 Ω for Ethernet, HDMI, USB‑HSIC

Target impedance tolerance on coupons is often ±10% using IPC‑TM‑650 2.5.5.7 TDR.

Geometry that hits those impedances

• 50 Ω microstrip on FR‑4 with 1 oz copper usually lands with dielectric h ≈ 0.10–0.20 mm and trace width w ≈ 0.18–0.40 mm, depending on Dk and soldermask.

• 50 Ω stripline with plane‑to‑plane spacing ≈ 0.20 mm and 0.5 oz inner copper typically needs w ≈ 0.10–0.14 mm.

• 90 Ω differential microstrip (USB2) at h ≈ 0.10–0.12 mm often uses w ≈ 0.18–0.22 mm and gap s ≈ 0.18–0.25 mm.

• 85 Ω differential stripline (PCIe) with ~0.20 mm plane spacing often uses w ≈ 0.10–0.12 mm and s ≈ 0.10–0.15 mm.

Always verify with a 2D field solver; copper roughness, mask, and resin Dk shift results by several ohms.

Example 4‑, 6‑, and 8‑layer stackups

4‑layer, 1.6 mm: L1 signal microstrip over 0.12 mm dielectric to L2 solid GND; 0.9–1.0 mm core to L3 solid PWR; 0.12 mm dielectric to L4 signal. Use outer microstrip for short RF and low‑layer‑count high‑speed, with tight L1‑L2 coupling for return paths.

6‑layer, 1.6 mm: L1 signal, L2 GND, L3 signal (stripline), L4 signal (stripline), L5 PWR, L6 GND. Keep L2/L3 close (e.g., 0.10–0.14 mm pressed) and L4/L5 close; place fast differential pairs on L3/L4 stripline for shielding.

8‑layer, 1.6–2.0 mm: Pair planes tightly around inner signal layers (e.g., L2 GND near L3, L6 GND near L5). Dedicate at least one continuous GND adjacent to every high‑speed layer. Backdrill through‑vias to remove stubs when link loss budgets are tight.

How do I pick dielectric thickness?

Start from interface targets and available prepreg glass styles. Choose the thinnest practical dielectric between signal and its nearest plane (0.08–0.15 mm is common) to reduce loop inductance. Then fit total thickness using cores and coarser weaves (e.g., 7628) away from critical layers to control cost.

HDI choices: 1+N+1 or 2+N+2?

• 1+N+1 uses one microvia layer per side into the first inner layer. Good for fine‑pitch BGAs and short via stubs.

• 2+N+2 stacks two microvia layers per side or uses staggered/stacked microvias to escape very dense BGAs. Resin‑filled and capped microvias enable via‑in‑pad. Backdrill any remaining through‑stub below the last connected layer.

• Blind/buried via strategy should keep a continuous reference for each transition and avoid anti‑pad gaps under fast pairs.

How to minimize skew and glass weave effects?

Select spread‑weave or mixed‑weave constructions (e.g., 2116 with 1080 rather than only 7628) for critical differential pairs. Route pairs with small bias angles (7–15°) and avoid long identical lengths on outer layers over a coarse weave. Match intra‑pair length within a few mils at the stackup’s effective velocity.

Power integrity and plane pairing

Use at least one uninterrupted GND plane. Pair PWR‑GND with a thin dielectric (≤0.10–0.15 mm) to raise interplane capacitance and push PDN resonances up. Do not split return planes under fast signals; if a split is unavoidable, route on a layer that references continuous ground.

Which standards apply?

• IPC‑2221/2226 for general and HDI stackup design rules

• IPC‑6012 for qualification and performance of rigid bare boards

• IPC‑4101 for base material specification

• IPC‑2152 for current‑carrying capacity and thermal rise guidance

• IPC‑TM‑650 methods (e.g., 2.5.5.7) for impedance coupon testing

Document the stackup in your fab notes with material callouts (IPC‑4101 slash sheet or laminate family), copper weights, dielectric thicknesses after lamination, target impedances and tolerances, and coupon requirements.

Manufacturing options at HyperPCB

Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria. RoHS and REACH compliance is supported for hazardous substance control. We return quotes within 24 hours and DFM feedback within 1 business day. HyperPCB operates an ISO 9001:2015 certified quality management system (certificate no. CN-2023-Q1156, SGS, valid until June 2027). Our partner factory AEGIS maintains ISO 9001:2015, ISO 14001:2015 and ISO 45001:2018 management systems, and also maintains ISO 13485:2016 for medical and IATF 16949 for automotive quality management. Our partner factory manufactures its own high‑frequency laminates and supplies RF PCB fabricators in China, including publicly listed PCB companies.

DFM tolerances you should budget

Dielectric thickness after press typically varies ±8–12% per ply; outer copper plating adds variability to trace thickness and width. Specify impedance tolerance (e.g., ±8–10%) and require coupon TDR. For fine‑pitch BGAs, confirm microvia aspect ratios and minimum pad/antipad sizes with your fabricator before freezing the stack.