PCB stackup generator: inputs, rules, and worked example stacks

A PCB stackup generator converts target impedances plus material/copper constraints into a specific layer order, dielectric schedule, and line/space that meet IPC-2141 class calculations within the stated impedance tolerance.

What does a stackup generator actually compute?

It solves for trace width (W) and pair spacing (S) from your dielectric thicknesses, Dk/Df versus frequency, and copper thickness, then places planes to control fields and crosstalk. For example, with FR-4 Dk ≈ 3.7–4.1 near 1 GHz and 35 µm outer copper, 50 Ω microstrip usually lands at W/H ≈ 1.7–1.9 where H is the dielectric to the reference plane; H = 0.18–0.20 mm gives W ≈ 0.32–0.36 mm by Hammerstad/Jensen. Symmetric 50 Ω stripline with 18–35 µm copper often solves near W/H ≈ 0.9–1.1 where H is the trace-center to each plane. The generator also applies plating adders (outer layers commonly gain ~8–12 µm), soldermask effects (LPI over microstrip lowers Z by ~2–4% around 50 Ω), and press-out of each glass style to predict finished dielectric thickness.

Which inputs matter the most?

• Impedance targets and tolerances per class (e.g., 50 Ω SE; 90/100 Ω diff at ±8–10%) and the bandwidth/rise time you care about

• Stack geometry and materials: layer count; FR-4 vs mid/low-loss; allowed glass styles (7628 is thick; 2116 mid; 1080/106 thin)

• Copper by layer and finish path: base copper (e.g., 18 or 35 µm) and expected outer-layer plating

• Minimum manufacturable line/space and via style; finished board thickness target (e.g., 1.60 mm)

• Test method and coupon plan (e.g., IPC-TM-650 2.5.5.7 TDR and per-class coupons)

Two notes affect accuracy more than most: use Dk/Df at your operating band (not just 1 MHz values) and lock specific glass plies so press-out can be modeled, e.g., 7628 press-out ≈ 0.18–0.20 mm per ply, 2116 ≈ 0.10–0.12 mm, 1080 ≈ 0.07–0.08 mm, 106 ≈ 0.05–0.06 mm depending on resin content.

Do you really need 50 Ω or 90/100 Ω diff?

Digital interfaces typically specify: 50 Ω single-ended; 90 Ω differential for USB 2.0 HS; 85 Ω differential for PCIe and USB 3.x; 100 Ω differential for Ethernet, SATA, DisplayPort, HDMI. For a first pass on FR-4, set microstrip differential S ≈ W for 90–100 Ω pairs, then refine with a 2D field solver (Hammerstad/Jensen, IPC-2141 approximations, or an EM solver). If microstrip is masked, expect a few percent lower Z; either narrow S slightly or widen W after simulation to hit target.

Worked 4-, 6-, and 8-layer examples

4-layer (≈1.6 mm, FR-4): L1 microstrip over L2 ground with 0.18–0.20 mm dielectric (e.g., 2116 or 2116+1080). 35 µm copper gives 50 Ω microstrip at W ≈ 0.32–0.36 mm. A 90 Ω differential microstrip often fits with W ≈ 0.18–0.22 mm and S ≈ 0.20–0.25 mm. L3 can be a solid power reference; L4 microstrip over L3 mirrors L1.

6-layer (≈1.6 mm, FR-4): L1 microstrip over L2 ground (0.18–0.22 mm). L3/L4 symmetric striplines between L2 and L5 planes; dielectric from trace center to each plane ≈ 0.18–0.24 mm. With 18 µm copper, 50 Ω stripline solves near W ≈ 0.16–0.20 mm; 100 Ω differential stripline commonly lands at W ≈ 0.10–0.14 mm, S ≈ 0.10–0.16 mm. L5 solid power; L6 microstrip over L5 similar to L1.

8-layer (1.6–2.0 mm, mid/low-loss optional): Keep L2 and L7 as solid grounds; route two stripline pairs (e.g., L3/L4 and L5/L6) with plane-to-plane spacing tight (≈0.15–0.22 mm) to confine fields and reduce broadside coupling. Use outer microstrips for breakouts/short runs and reserve the inner striplines for long high-speed links.

How do you verify tolerances?

Request material data near your operating band (Dk, Df, copper roughness) and the press-out thickness for each ply. Model min/max stacks with dielectric ±10% and copper ±5–10 µm, include outer-layer plating adders, and re-simulate impedances. State mask type and whether traces are covered or opened in RF zones. Add per-class impedance coupons and define the measurement method/frequency (e.g., IPC-TM-650 2.5.5.7 TDR at a stated rise time) so acceptance matches your targets.

Standards and certifications we support

Boards can be built and inspected to IPC Class 2 or Class 3 acceptance criteria, and RoHS/REACH compliance is supported. Our quality management system is ISO 9001:2015 certified (SGS certificate CN-2023-Q1156, valid until June 2027). For regulated markets, our partner factory AEGIS maintains ISO 9001:2015, ISO 14001:2015 and ISO 45001:2018, plus ISO 13485:2016 and IATF 16949. AEGIS also manufactures its own high-frequency laminates and supplies RF PCB fabricators in China, including publicly listed companies.