PCB stackup: numbers for 50/90/100 Ω, material picks, and two proven builds

Stackup sets impedance, loss, and PDN targets

Set dielectric heights, copper weights, and plane order so key nets meet 50 Ω single‑ended and 90/100 Ω differential within a defined tolerance, and so channel insertion loss at the interface Nyquist rate stays inside budget. Keep return planes adjacent to routing layers to limit EMI and crosstalk, and size overall thickness for mechanical constraints.

Which materials and Dk/Df fit 3–28 Gbps?

Standard FR‑4: εr ≈ 3.7–4.2 at 1 GHz, tanδ ≈ 0.012–0.018. Practical reaches at 10 Gbps NRZ (Nyquist 5 GHz): about 5–7 in (125–180 mm) for internal stripline if you reserve ≈6 dB of the link budget for bare dielectric/conductor loss, because typical stripline loss is ≈0.8–1.0 dB/in at 5 GHz with standard foil roughness.

Low‑loss FR‑4: εr ≈ 3.5–3.8, tanδ ≈ 0.005–0.009. At 5 GHz, stripline loss often lands ≈0.35–0.5 dB/in, extending that ≈6 dB allocation to ≈12–17 in (300–430 mm).

Very low‑loss (e.g., εr ≈ 3.2–3.5, tanδ ≈ 0.0015–0.003): ≈0.18–0.30 dB/in at 5 GHz; the same ≈6 dB allocation supports ≈20–33 in (500–840 mm). At 25–28 Gbps NRZ (Nyquist 12.5–14 GHz), conductor and dielectric loss roughly 1.6–2.5× higher than at 5 GHz; scale reaches down accordingly. Soldermask (εr ≈ 3.2–3.6, 10–20 µm) reduces microstrip impedance by ≈2–4 Ω; include it in the solver.

How close do closed‑form equations get?

Use a 2D field solver for sign‑off. For first‑pass sizing, closed forms are within a few ohms if you feed realistic h, t, and mask. Microstrip: Z0 ≈ 87/√(εr+1.41) · ln[5.98h/(0.8w+t)]. Symmetric stripline: Z0 ≈ 60/√εr · ln[1.9b/(0.8w+t)]. Here h is dielectric height to the plane, b is plane‑to‑plane spacing, w is trace width, t is copper thickness. Differential: 90–100 Ω often occurs near s ≈ 0.8–1.2·w for microstrip/stripline, but calculate with actual stack and soldermask.

4‑layer, 1.6 mm example with real widths

L1: 35 µm Cu (signals)

Prepreg: 2116 + 1080 ≈ 0.19 mm (εr ≈ 3.9)

L2: 18 µm Cu (GND)

Core: ≈ 0.80 mm (εr ≈ 3.9)

L3: 18 µm Cu (PWR)

Prepreg: 2116 + 1080 ≈ 0.19 mm (εr ≈ 3.9)

L4: 35 µm Cu (signals)

Sizing: a 50 Ω L1 microstrip with h ≈ 0.19 mm and t = 35 µm yields w ≈ 0.34–0.38 mm from the microstrip formula; a 90 Ω differential pair of that width typically uses s ≈ 0.25–0.30 mm. Expect a further ≈2–4 Ω decrease from soldermask; verify with a solver and TDR coupons.

6‑layer, 1.6 mm example for low EMI

L1: 35 µm Cu (signals)

Prepreg: 1080 + 2116 ≈ 0.18 mm → L2

L2: 18 µm Cu (GND)

Core: ≈ 0.36 mm → L3

L3: 18 µm Cu (signals, symmetric stripline)

Core: ≈ 0.36 mm → L4

L4: 18 µm Cu (signals, symmetric stripline)

Prepreg: 2116 + 1080 ≈ 0.18 mm → L5

L5: 18 µm Cu (PWR)

Prepreg: ≈ 0.16 mm → L6

L6: 35 µm Cu (signals)

Sizing: with b ≈ 0.36 mm and t = 18 µm, 50 Ω stripline often falls at w ≈ 0.16–0.18 mm; 100 Ω differential commonly uses s ≈ 0.18–0.24 mm at that width. Place stitched grounds near every transition via to keep return continuity.

When is low‑loss laminate worth it?

If your channel budget from package‑to‑package reserves ≤8–10 dB at Nyquist for bare interconnect, compute copper+dielectric loss per inch at that frequency (solver or vendor data). For 10 Gbps NRZ, standard FR‑4 limits stripline to roughly 6–8 in before equalization margins get tight; if you need 12–16 in on‑board without retimers, low‑loss FR‑4 is typically the inflection point. For 25–28 Gbps links longer than ≈4–6 in of stripline, very low‑loss saves multiple dB and simplifies equalization. Always confirm with S‑parameter stacks that include roughness and plating models.

Crosstalk and weave‑induced skew control

For external microstrip, spacing s ≥ 3h generally holds far‑end crosstalk to low single‑digit percent over several inches. For internal stripline, s ≥ 3w is a practical floor. To limit differential skew from glass weave (e.g., 106/1080), prefer spread‑glass (e.g., 3313/2116 spread), keep pairs tight, and use a slight 5–10° route angle relative to the weave. Match intra‑pair length to ≤1 ps/in differential (≈150 µm/in) where SERDES CDR margin is tight.

Vias, stubs, and return current continuity

A quarter‑wave stub at 5 GHz in FR‑4 is ≈7.6 mm; keep stubs well below ≈3 mm via backdrill, blind/buried vias, or filled via‑in‑pad to avoid resonances. Place a ground via within ≈0.5–1.0 mm of each high‑speed signal via when changing reference planes so the return path remains compact. Use short anti‑pads and teardrops to control pad/capture inductance.

What must go in the fab package?

• Layer table with each copper weight and each dielectric thickness and target εr/tanδ

• Controlled‑impedance table (e.g., 50 Ω SE, 90/100 Ω diff) with tolerance; ±10% is common

• Field‑solver reports with soldermask assumptions and copper‑roughness model notes

• Coupon and test callouts (e.g., IPC‑TM‑650 2.5.5.7), and IPC‑6012 class in the fab notes

• Weave preference (spread glass), surface finish, soldermask thickness, and acceptance limits

Also consult IPC‑2152 for current‑related thermal limits when setting copper weights.

Manufacturing and acceptance criteria

Call out IPC‑6012 Class 2 or Class 3 as required and specify RoHS/REACH compliance if needed. Provide impedance coupon requirements and the target TDR measurement conditions so results are traceable to routing environments.

Working with HyperPCB on stackups

HyperPCB operates an ISO 9001:2015 certified quality management system (certificate no. CN‑2023‑Q1156, issued by SGS, valid until June 2027). Quotes are returned within 24 hours and DFM feedback within 1 business day. Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria, and RoHS/REACH compliance is supported. Our partner factory AEGIS maintains ISO 9001:2015, ISO 14001:2015 and ISO 45001:2018, plus ISO 13485:2016 and IATF 16949. Our partner factory also manufactures its own high‑frequency laminates and supplies RF PCB fabricators in China, including publicly listed PCB companies.