Pre‑production PCB routing review: files, numeric checks, fast DFM

Scope of a routing DFM review

Submit fabrication data; we return DFM feedback within 1 business day. Checks typically cover drill‑to‑copper clearance (outer layers ≥0.25 mm, inner ≥0.20 mm), via annular ring (≥0.10 mm; ≥0.15 mm preferred on fine drills), solder mask slivers (≥0.10 mm/4 mil), copper thieving and pattern balance to limit bow/twist per IPC‑6012 (≤0.75% Class 2, ≤0.5% Class 3), panelization and break‑offs, and that fab notes align with IPC Class 2 or Class 3 acceptance criteria. We also confirm impedance targets are documented and consistent with the stackup and materials.

Which files should I send for DFM?

• Gerber RS‑274X or ODB++ with clear layer naming and a mechanical outline

• NC drill and route (Excellon), plated vs non‑plated identified, tool table included

• IPC‑356 netlist for connectivity cross‑check

• Layer stackup with dielectric thicknesses (e.g., 0.10 mm 2116, 0.18 mm 7628), copper weights (e.g., 35 µm outer, 17 µm inner), and laminate Dk/Df

• Fabrication notes: surface finish, mask/legend colors, impedance targets and tolerance (e.g., 50 Ω ±10%, 90/100 Ω diff ±10%)

• Panel drawing or panelization request with rail width (e.g., 5–10 mm), fiducials, and tooling holes

• Any controlled‑depth routing, backdrill maps, blind/buried via definitions, or special keepouts

15‑minute routing checks you can do

Return paths: keep high‑speed traces over a continuous reference plane; when changing layers, place stitching vias within 2–3 mm of the signal via. Avoid crossing plane splits; if unavoidable, use a tightly‑coupled capacitive bridge adjacent to the transition.

Differential pairs: hold constant trace width and gap; minimize neck‑downs and keep intra‑pair length skew below 5 ps (about 0.75–1.0 mm on FR‑4) for multi‑Gb/s links. Use symmetric via transitions and specify antipads large enough to keep pair impedance stable while meeting annular‑ring rules.

Spacing and creepage: for 3.3–5 V logic, 0.10–0.15 mm (4–6 mil) conductor spacing on outer layers is common; for 12 V use ≥0.20 mm; always verify against IPC‑2221 and any product‑safety standard that applies to your design.

Pads, masks, and legends: keep solder mask dams ≥0.10 mm (4 mil) for 0402; avoid silkscreen on exposed copper; add teardrops at fine vias and neck‑downs to improve drill and etch margin. Use thermal spokes (e.g., four at 0.20–0.30 mm width) on through‑hole pads tied to planes for solderability.

Copper balance: distribute copper to avoid large bare areas opposing heavy copper; this reduces bow/twist and etch bias. Plan panel‑level thieving if pattern density varies widely across the array.

How do I sanity‑check impedance and stackup?

Lock stackup before tuning routing. Typical FR‑4 Dk at 1 GHz is around 3.7–4.2; always use your laminate’s datasheet in a field solver. Example starting points:

• 4‑layer with outer microstrip over a plane and inner solid planes: with 0.10 mm dielectric (e.g., 2116 prepreg) and 35 µm copper, 50 Ω microstrip is often ~0.15–0.20 mm (6–8 mil) wide; a 100 Ω differential microstrip can be ~0.13–0.16 mm traces with the same ~0.13–0.16 mm gap.

• With a thicker 0.18 mm dielectric (e.g., 7628), 50 Ω microstrip is typically ~0.28–0.36 mm (11–14 mil); 100 Ω differential microstrip may be ~0.20–0.25 mm traces with ~0.20–0.25 mm gap.

• Symmetric stripline between two planes: with ~0.20 mm dielectric and 17 µm copper, 50 Ω stripline often lands ~0.18–0.23 mm (7–9 mil); 100 Ω differential can be ~0.12–0.15 mm traces with ~0.15–0.20 mm gap.

Document targets commonly used in industry—50 Ω single‑ended; 85 Ω differential (PCIe/USB 3.x); 90 Ω differential (USB 2.0 D+/D‑); 100 Ω differential (Ethernet, HDMI, LVDS)—and state tolerance (±10% typical) in fab notes so impedance control is verified during DFM.

What routing issues most often get flagged?

Mask slivers below ~0.10 mm that can fracture; via annular rings too small for registration margin (increase pad or add teardrops); through‑hole aspect ratio beyond ~8–10:1 (e.g., 1.6 mm board with ≤0.20 mm finished drill is ~8:1; smaller drills may require additional lamination or backdrill on fast nets); acute copper angles and isolated islands that etch poorly; missing panel rails, fiducials, or awkward break‑tab placement that hinders assembly and test. Silkscreen over pads is always clipped.

Certifications and build options you can request

Our quality management system is ISO 9001:2015 certified (certificate no. CN-2023-Q1156, issued by SGS, valid until June 2027). Quotes are returned within 24 hours and DFM feedback within 1 business day. Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria, and RoHS/REACH compliance is supported. Our partner factory AEGIS maintains ISO 9001:2015, ISO 14001:2015 and ISO 45001:2018 systems, plus ISO 13485:2016 and IATF 16949. AEGIS also manufactures its own high‑frequency laminates and supplies RF PCB fabricators in China, including publicly listed PCB companies.