SDRAM, LCD, and Ethernet layout review checklist and routing rules

Here is a practical checklist and routing rules to review SDRAM, LCD, and Ethernet layouts before release.

SDRAM timing, topology, and matching rules

• Use fly‑by for DDR2/DDR3 address/command/clock; point‑to‑point for SDR/LPDDR with short stubs. Keep any stubs on DQ/DQS under 50 mil.

• Derive length budgets from datasheet timing. Convert time to distance with ~150 ps/in (≈6 ps/mm) for FR‑4 stripline. Example: 20 ps skew ≈ 3.3 mm, 50 ps ≈ 8.3 mm.

• Typical starting targets: intra‑byte DQ skew ≤ 20 ps (~3 mm); DQS‑to‑byte skew ≤ 25–50 ps (4–8 mm). Tighten to vendor guidance if provided.

• Termination: SDR often benefits from 22–33 Ω series resistors at the controller for address/command/clock; DDR2/3 typically uses ODT for DQ and VTT (≈50 Ω to VTT) for address/command. Place resistors within 200 mil of the driver.

• Route DQS with the associated DQ byte as a phase‑matched group; avoid layer transitions on DQS if possible. If vias are unavoidable, make them symmetric across the group and back‑drill if stubs exceed 10–15 mil.

Ethernet PHY, magnetics, and pair routing rules

• 10/100/1000BASE‑T MDI pairs: 100 Ω differential (±10%). Keep intra‑pair length mismatch ≤ 5 mil and inter‑pair within 100 mil to the magnetics.

• Keep differential pairs on one layer with a continuous reference plane; avoid crossing plane splits. Minimize and balance vias; if one trace takes a via, give its mate an identical via.

• Place the magnetics close to the RJ45. Route PHY → magnetics first; place termination per PHY/magnetics datasheet adjacent to the PHY pins. Keep the route from magnetics to RJ45 short and direct.

• RMII/MII/GMII digital lines: keep trace lengths reasonable (e.g., < 1500 mil) and match data to the reference clock within 50–100 mil unless the PHY datasheet specifies otherwise.

LCD interfaces: RGB TTL and MIPI DSI

• RGB TTL (e.g., 18/24‑bit): match data and control to the pixel clock within the timing budget. As a conservative target, keep data‑to‑CLK skew ≤ 200 mil; tighter if tSU/tH is small. Keep the pixel clock clean: short, direct, isolated from fast edges on other nets.

• MIPI DSI (D‑PHY HS): 100 Ω differential unless the panel vendor calls for 90 Ω. Keep intra‑pair skew ≤ 5 mil, pair‑to‑pair within 50–100 mil. Maintain spacing from other aggressors (≥ 3× the intra‑pair gap) and avoid stubs, test pads, and stiching breaks in the return path.

Impedance and stack‑up examples that usually work

• Target impedances: 50 Ω single‑ended, 100 Ω differential for Ethernet, LVDS, and most MIPI links; 90 Ω differential only when a spec explicitly requires it.

• A practical 6‑layer starting stack (symmetric): L1 Sig, L2 GND, L3 Sig (stripline), L4 Sig (stripline), L5 PWR (or GND), L6 Sig. With FR‑4 (εr ≈ 3.8–4.1), 0.5 oz copper, and ~4 mil dielectric above/below the stripline layers, 4 mil stripline traces are near 50 Ω; 4/6 mil (w/gap) gives ~100 Ω differential. Validate with your fab’s field solver.

• For microstrip on outer layers, confirm with your fabricator’s stack library; dielectric height dominates. Do not mix reference planes under a controlled‑impedance trace.

Power integrity at SDRAM, PHY, and display drivers

• Compute target impedance: Ztarget = ΔV/ΔI. Example: 1.2 V rail, 2 A step, 3% ripple (36 mV) → Ztarget ≈ 18 mΩ. Distribute MLCCs to meet this across the operating band.

• Place one 0.1 µF per power pin (or per pair) at SDRAM/PHY, plus several 1 µF nearby and a few bulk parts (4.7–22 µF) per rail. Use short, wide connections and dedicated return vias (via‑in‑pad for fine‑pitch BGAs is ideal).

• Isolate noisy rails (PHY TX, LED backlight drivers) with LC filters or ferrite beads sized by impedance vs frequency, not DC resistance alone.

EMC, return paths, and connector zones

• Keep high‑speed loops tight with an unbroken reference plane. Stitch ground near layer transitions of DQ/DQS, MDI pairs, and LCD pairs.

• At the RJ45, follow the magnetics datasheet for center‑tap decoupling and any common‑mode dump network to chassis. Place TVS arrays at the connector with very short returns to chassis/earth.

• For FPC display connectors, provide a solid reference under the high‑speed pins, add ground pins between groups, and keep hot‑plug/ESD paths short and local.

What should be checked before requesting a review?

• Controlled impedances set for all relevant net classes (50 Ω SE, 100 Ω diff, any 90 Ω if required)

• Length rules entered for SDRAM DQ/DQS and address/command, RMII/GMII, and LCD groups

• Reference planes continuous; no high‑speed trace crossing splits or plane voids

• Differential pairs length‑matched and phase‑matched; no asymmetrical via count

• Termination and series damping values placed and located near drivers/receivers

• Decoupling fitted per pin with keep‑in distances respected; PDN vias are short and numerous

• Magnetics/RJ45 placement and keepouts validated; ESD/TVS paths verified

• Via stubs assessed; back‑drill plan for long stubs on fast nets

What files help us review quickly?

Provide the stack‑up (materials, copper weights, dielectric thickness), impedance targets, constraint rules, schematics, and a manufacturing export (ODB++ preferred; Gerbers + drill + netlist also work). If available, include IBIS/AMI models for memory and PHY, and any vendor‑specific timing budgets you are enforcing.

Manufacturing and compliance notes

Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria. RoHS and REACH compliance is supported for hazardous substance control. Our quality management system is ISO 9001:2015 certified (certificate CN‑2023‑Q1156 by SGS, valid to June 2027).