Should a 6‑layer PCB use a thin middle prepreg between L3–L4?

Yes—use a thin middle prepreg between L3 (PWR) and L4 (GND) to cut loop inductance and lower PDN impedance; do not use an ultra‑thin dielectric if both L3 and L4 are signal layers.

When does a thin mid‑dielectric help?

It helps when you want embedded decoupling between a power–ground plane pair, to suppress plane‑pair cavity resonances in the 10–500 MHz band, and to confine fields for cleaner return paths on adjacent inner signal layers. You also gain headroom on EMI because the return loop area shrinks.

How thin is thin for the center pair?

For standard FR‑4, a pressed dielectric of about 60–120 µm between PWR and GND is practical. Below ~50 µm, a single 106 ply can starve resin and print weave; above ~150 µm, the inductance/capacitance benefits drop quickly. Keep the stack symmetric in copper and dielectric to control bow/warp.

What do you gain numerically?

Plane‑pair sheet inductance Ls ≈ μ0·h. With h = 0.10 mm, Ls ≈ 126 pH/square. Plane‑pair capacitance density C/A = ε0·εr/h; with εr ≈ 4 and h = 0.10 mm, that’s ≈ 228 pF per square inch. This moves the PDN parallel‑plate resonance up and lowers mid‑band impedance, reducing the burden on discrete MLCCs for high‑di/dt loads.

Which glass styles fit 60–120 µm?

Resin‑richer, fine weaves or stacks such as 2×106, 106+1080, or 2×1080 commonly press to 60–120 µm in the center pair. Avoid single‑ply 106 below ~60 µm. For thicker cores elsewhere to meet a 1.55–1.60 mm build, 2116 or 7628 are typical choices.

Impedance impact you can verify

Tighter planes shift Z0 on adjacent signal layers. For FR‑4 (Dk ≈ 3.8–3.9 @ 1 GHz) and 35 µm copper: a symmetric stripline with h ≈ 0.10 mm to planes on both sides hits 50 Ω near w ≈ 0.12 mm and 100 Ω differential near w ≈ 0.12 mm, s ≈ 0.12 mm (Wheeler/Hammerstad). A microstrip over h ≈ 0.10 mm reaches 50 Ω around w ≈ 0.18–0.20 mm; 90–100 Ω differential often lands near w ≈ 0.18 mm, s ≈ 0.18–0.22 mm depending on soldermask and copper roughness. Always re‑solve after locking glass style and copper weight; mask and roughness shift Z0 by a few ohms.

Will a thin center dielectric hurt manufacturability?

Used correctly, no. Ultra‑thin plies concentrate resin, so balance copper to avoid squeeze‑out during lamination. Respect CAF risk by keeping minimum dielectric between opposing copper features in the 75–100 µm range for standard FR‑4 when long humid‑bias life is required. Drilling remains practical: a 1.6 mm board with 0.20 mm finished hole is ~8:1 aspect ratio; staying ≤ 8–10:1 is a common target for plated through‑holes without HDI.

Where should signals sit around the thin pair?

Place the thin dielectric strictly between PWR and GND to maximize embedded capacitance. Route high‑speed signals on L3‑adjacent and L4‑adjacent layers so each sees a solid, close reference. If two inner signal layers must face each other, do not put the ultra‑thin dielectric between them—coupling and crosstalk rise sharply.

Recommended 6‑layer stacks in words

EMI/PDN‑focused: L1 signal (microstrip) over L2 GND; center L3 PWR and L4 GND tightly coupled (≈ 60–120 µm); L5 signal (stripline) references L4; L6 signal (microstrip) references L5/inner plane via stitching. High‑speed‑centric: L1 signal, L2 GND, L3/L4 striplines, L5 GND, L6 signal; only use a thin dielectric between a PWR–GND pair, not between the two stripline layers.

DFM checklist

• Call out center dielectric target (e.g., L3–L4 press‑out 0.08–0.10 mm) and acceptable glass stacks (e.g., 106+1080)

• Specify copper weights per layer and total thickness target (e.g., 1.55–1.60 mm)

• Provide impedance goals and tolerances (e.g., 50 Ω SE ±10%, 100 Ω Diff ±10%)

• Identify the PWR–GND pair and acceptable laminate Dk/Df ranges for substitutions

• Add stitching vias within ~2–3 mm where references change to close return loops

Manufacturing and compliance you can expect

Boards can be built and inspected to IPC Class 2 or Class 3 acceptance criteria, and RoHS/REACH compliance is supported. Quotes are returned within 24 hours and DFM feedback is provided within 1 business day. Our quality management system is ISO 9001:2015 certified (certificate CN-2023-Q1156, SGS, valid to June 2027).

Example center choice you can reuse

For a 1.60 mm build targeting low PDN impedance, set L3–L4 press‑out to 0.10 mm using 106+1080, make L3 = PWR and L4 = GND, use 1 oz finished copper on outers and 0.5 oz on inners, then solve for L1 microstrip 50 Ω at w ≈ 0.19 mm over 0.10–0.12 mm dielectric and L5 stripline 50 Ω at w ≈ 0.12 mm with ≈ 0.10–0.12 mm spacing to planes. This yields about 126 pH/square sheet inductance and ~228 pF/in² plane‑pair capacitance at the center.